{"id":"https://openalex.org/W2020338584","doi":"https://doi.org/10.1109/tc.1980.1675635","title":"Theory and Design of Mixed-Mode Sequential Machines","display_name":"Theory and Design of Mixed-Mode Sequential Machines","publication_year":1980,"publication_date":"1980-07-01","ids":{"openalex":"https://openalex.org/W2020338584","doi":"https://doi.org/10.1109/tc.1980.1675635","mag":"2020338584"},"language":"en","primary_location":{"id":"doi:10.1109/tc.1980.1675635","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1980.1675635","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","0016-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5097403642","display_name":"Dervisoglu","orcid":null},"institutions":[{"id":"https://openalex.org/I140172145","display_name":"University of Connecticut","ror":"https://ror.org/02der9h97","country_code":"US","type":"education","lineage":["https://openalex.org/I140172145"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dervisoglu","raw_affiliation_strings":["Department of Electrical Engineering and Computer Science, Computer Science Division, University of Connecticut","Department of Electrical Engineering and Computer Science, Computer Science Division, University of Connecticut, Storrs, CT, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering and Computer Science, Computer Science Division, University of Connecticut","institution_ids":["https://openalex.org/I140172145"]},{"raw_affiliation_string":"Department of Electrical Engineering and Computer Science, Computer Science Division, University of Connecticut, Storrs, CT, USA","institution_ids":["https://openalex.org/I140172145"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5012029502","display_name":"Sholl","orcid":null},"institutions":[{"id":"https://openalex.org/I140172145","display_name":"University of Connecticut","ror":"https://ror.org/02der9h97","country_code":"US","type":"education","lineage":["https://openalex.org/I140172145"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sholl","raw_affiliation_strings":["Department of Electrical Engineering and Computer Science, Computer Science Division, University of Connecticut, Storrs, CT, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering and Computer Science, Computer Science Division, University of Connecticut, Storrs, CT, USA","institution_ids":["https://openalex.org/I140172145"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I140172145"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.1973466,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":"C-29","issue":"7","first_page":"639","last_page":"648"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9951000213623047,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11125","display_name":"Petri Nets in System Modeling","score":0.9912999868392944,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/realization","display_name":"Realization (probability)","score":0.8031549453735352},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.7976076006889343},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7690229415893555},{"id":"https://openalex.org/keywords/representation","display_name":"Representation (politics)","score":0.6139218807220459},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.596568763256073},{"id":"https://openalex.org/keywords/finite-state-machine","display_name":"Finite-state machine","score":0.510298490524292},{"id":"https://openalex.org/keywords/mode","display_name":"Mode (computer interface)","score":0.47167596220970154},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.37962228059768677},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3330385088920593},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3210563659667969},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3075314164161682},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11361095309257507},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.10953328013420105},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.08198785781860352}],"concepts":[{"id":"https://openalex.org/C2781089630","wikidata":"https://www.wikidata.org/wiki/Q21856745","display_name":"Realization (probability)","level":2,"score":0.8031549453735352},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.7976076006889343},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7690229415893555},{"id":"https://openalex.org/C2776359362","wikidata":"https://www.wikidata.org/wiki/Q2145286","display_name":"Representation (politics)","level":3,"score":0.6139218807220459},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.596568763256073},{"id":"https://openalex.org/C167822520","wikidata":"https://www.wikidata.org/wiki/Q176452","display_name":"Finite-state machine","level":2,"score":0.510298490524292},{"id":"https://openalex.org/C48677424","wikidata":"https://www.wikidata.org/wiki/Q6888088","display_name":"Mode (computer interface)","level":2,"score":0.47167596220970154},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.37962228059768677},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3330385088920593},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3210563659667969},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3075314164161682},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11361095309257507},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10953328013420105},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.08198785781860352},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C199539241","wikidata":"https://www.wikidata.org/wiki/Q7748","display_name":"Law","level":1,"score":0.0},{"id":"https://openalex.org/C17744445","wikidata":"https://www.wikidata.org/wiki/Q36442","display_name":"Political science","level":0,"score":0.0},{"id":"https://openalex.org/C94625758","wikidata":"https://www.wikidata.org/wiki/Q7163","display_name":"Politics","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tc.1980.1675635","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1980.1675635","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","0016-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5199999809265137,"display_name":"Peace, Justice and strong institutions","id":"https://metadata.un.org/sdg/16"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1966436625","https://openalex.org/W1982070750","https://openalex.org/W2005620514","https://openalex.org/W2033724727","https://openalex.org/W2049367172","https://openalex.org/W2062857500","https://openalex.org/W2110209760","https://openalex.org/W2150664038","https://openalex.org/W2164677009"],"related_works":["https://openalex.org/W2116677773","https://openalex.org/W2022544890","https://openalex.org/W2394097730","https://openalex.org/W2043523297","https://openalex.org/W2475378634","https://openalex.org/W2155261584","https://openalex.org/W2113405914","https://openalex.org/W2584231425","https://openalex.org/W4312353617","https://openalex.org/W4232940367"],"abstract_inverted_index":{"A":[0],"mixed":[1],"mode":[2],"sequential":[3],"machine":[4],"(MSM)":[5],"is":[6,28,61,92],"defined":[7],"as":[8,50],"a":[9,39,96],"representation":[10,27],"in":[11,38,68],"which":[12,69,99],"both":[13,34,101],"synchronous":[14],"(clocked)":[15],"and":[16,85,103],"asynchronous":[17,70],"(unclocked)":[18],"state":[19,81,83],"transitions":[20,37,105],"are":[21,72,87],"allowed.":[22],"The":[23,59,78],"intent":[24],"of":[25,36,46,80,95],"the":[26,44,56,93],"to":[29,32,54,106],"allow":[30],"designers":[31],"consider":[33],"types":[35],"single":[40],"structure,":[41],"thereby":[42],"promoting":[43],"use":[45],"LSI":[47],"devices":[48],"such":[49],"ROM's":[51],"or":[52],"PLA's":[53],"resolve":[55],"realization":[57,86],"question.":[58],"approach":[60],"thus":[62],"different":[63],"from":[64],"conventional":[65],"design":[66],"methods,":[67],"problems":[71,79],"treated":[73],"separately":[74],"with":[75],"separate":[76],"devices.":[77],"reduction,":[82],"assignment,":[84],"covered.":[88],"Of":[89],"particular":[90],"note":[91],"development":[94],"ROM":[97],"implementation,":[98],"allows":[100],"clocked":[102],"unclocked":[104],"occur.":[107]},"counts_by_year":[{"year":2012,"cited_by_count":2}],"updated_date":"2026-07-07T14:30:12.667765","created_date":"2025-10-10T00:00:00"}