{"id":"https://openalex.org/W1974658702","doi":"https://doi.org/10.1109/tc.1980.1675534","title":"Design Considerations for Single-Chip Computers of the Future","display_name":"Design Considerations for Single-Chip Computers of the Future","publication_year":1980,"publication_date":"1980-02-01","ids":{"openalex":"https://openalex.org/W1974658702","doi":"https://doi.org/10.1109/tc.1980.1675534","mag":"1974658702"},"language":"en","primary_location":{"id":"doi:10.1109/tc.1980.1675534","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1980.1675534","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5112774301","display_name":"Patterson","orcid":null},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Patterson","raw_affiliation_strings":["Computer Science Division, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA, USA"],"affiliations":[{"raw_affiliation_string":"Computer Science Division, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA, USA","institution_ids":["https://openalex.org/I95457486"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5063997642","display_name":"Sequin","orcid":null},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sequin","raw_affiliation_strings":["Computer Science Division, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA, USA"],"affiliations":[{"raw_affiliation_string":"Computer Science Division, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA, USA","institution_ids":["https://openalex.org/I95457486"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5112774301"],"corresponding_institution_ids":["https://openalex.org/I95457486"],"apc_list":null,"apc_paid":null,"fwci":13.6371,"has_fulltext":false,"cited_by_count":50,"citation_normalized_percentile":{"value":0.99134948,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"C-29","issue":"2","first_page":"108","last_page":"116"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.994700014591217,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7891737222671509},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6628563404083252},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.6222414374351501},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5760019421577454},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5472897291183472},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4649884104728699},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.44043800234794617},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.43694227933883667},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.42805758118629456},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.42041391134262085},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4185813367366791},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3795218765735626},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.32626622915267944},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1306646168231964},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.09407490491867065},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.08970239758491516},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.08486071228981018}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7891737222671509},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6628563404083252},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.6222414374351501},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5760019421577454},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5472897291183472},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4649884104728699},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.44043800234794617},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.43694227933883667},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.42805758118629456},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.42041391134262085},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4185813367366791},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3795218765735626},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.32626622915267944},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1306646168231964},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.09407490491867065},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.08970239758491516},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.08486071228981018},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tc.1980.1675534","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1980.1675534","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320310466","display_name":"Universit\u00e4t Basel","ror":"https://ror.org/02s6k3f65"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":30,"referenced_works":["https://openalex.org/W1497601207","https://openalex.org/W1664534452","https://openalex.org/W1666015432","https://openalex.org/W1941301772","https://openalex.org/W1969046545","https://openalex.org/W1970851108","https://openalex.org/W1971424755","https://openalex.org/W1990242331","https://openalex.org/W1995918165","https://openalex.org/W1996790705","https://openalex.org/W2000877408","https://openalex.org/W2008494888","https://openalex.org/W2019744639","https://openalex.org/W2041110543","https://openalex.org/W2053162270","https://openalex.org/W2061345213","https://openalex.org/W2080354905","https://openalex.org/W2093307539","https://openalex.org/W2103522716","https://openalex.org/W2109072691","https://openalex.org/W2132729131","https://openalex.org/W2133045033","https://openalex.org/W2135461915","https://openalex.org/W2142629858","https://openalex.org/W2143195248","https://openalex.org/W2144481293","https://openalex.org/W4249925044","https://openalex.org/W4253674545","https://openalex.org/W4285719527","https://openalex.org/W6675409621"],"related_works":["https://openalex.org/W4283025278","https://openalex.org/W61292821","https://openalex.org/W2082432309","https://openalex.org/W817174743","https://openalex.org/W2050492524","https://openalex.org/W2998315020","https://openalex.org/W2104790384","https://openalex.org/W1976665945","https://openalex.org/W3016208414","https://openalex.org/W2098218272"],"abstract_inverted_index":{"In":[0],"the":[1,27,109,128,133,140],"mid":[2],"1980's":[3],"it":[4],"will":[5,115],"be":[6,116],"possible":[7],"to":[8,132],"put":[9],"a":[10,20,92,103,117,121,143],"million":[11],"devices":[12],"(transistors":[13],"or":[14],"active":[15],"MOS":[16],"gate":[17],"electrodes)":[18],"onto":[19],"single":[21,122],"silicon":[22,30],"chip.":[23,123],"General":[24],"trends":[25],"in":[26,47],"evolution":[28],"of":[29,112,127],"integrated":[31,60],"circuits":[32,41,61],"are":[33,42,50,62],"reviewed":[34],"and":[35,53,89,96,139],"design":[36,68],"constraints":[37],"for":[38,55,80,85,108],"emerging":[39],"VLSI":[40],"analyzed.":[43],"Desirable":[44],"architectural":[45],"features":[46,70],"modern":[48],"computers":[49],"then":[51],"discussed":[52],"consequences":[54],"an":[56,73],"implementation":[57],"with":[58],"large-scale":[59],"investigated.":[63],"The":[64],"resulting":[65],"recommended":[66],"processor":[67],"includes":[69],"such":[71],"as":[72],"on-chip":[74],"memory":[75,144],"hierarchy,":[76],"multiple":[77],"homogeneous":[78],"caches":[79],"enhanced":[81],"execution":[82],"parallelism,":[83],"support":[84],"complex":[86],"data":[87],"structures":[88],"high-level":[90],"languages,":[91],"flexible":[93],"instruction":[94],"set,":[95],"communication":[97],"hardware.":[98],"It":[99],"is":[100,137,142],"concluded":[101],"that":[102],"viable":[104],"modular":[105],"building":[106],"block":[107],"next":[110],"generation":[111],"computing":[113],"systems":[114],"self-contained":[118],"computer":[119],"on":[120],"A":[124],"tentative":[125],"allocation":[126],"one":[129],"milion":[130],"transistors":[131],"various":[134],"functional":[135],"blocks":[136],"given,":[138],"result":[141],"intensive":[145],"design.":[146]},"counts_by_year":[{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}