{"id":"https://openalex.org/W1841996692","doi":"https://doi.org/10.1109/tc.1980.1675500","title":"Dual-Mode Logic for Function-Independent Fault Testing","display_name":"Dual-Mode Logic for Function-Independent Fault Testing","publication_year":1980,"publication_date":"1980-11-01","ids":{"openalex":"https://openalex.org/W1841996692","doi":"https://doi.org/10.1109/tc.1980.1675500","mag":"1841996692"},"language":"en","primary_location":{"id":"doi:10.1109/tc.1980.1675500","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1980.1675500","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5112624906","display_name":"Dasgupta","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Dasgupta","raw_affiliation_strings":["IBM Data Systems Division"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IBM Data Systems Division","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002591576","display_name":"Hartmann","orcid":null},"institutions":[{"id":"https://openalex.org/I70983195","display_name":"Syracuse University","ror":"https://ror.org/025r5qe02","country_code":"US","type":"education","lineage":["https://openalex.org/I70983195"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hartmann","raw_affiliation_strings":["School of Computer and Information Science, Syracuse University, Syracuse, NY, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Computer and Information Science, Syracuse University, Syracuse, NY, USA","institution_ids":["https://openalex.org/I70983195"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109900056","display_name":"Rudolph","orcid":null},"institutions":[{"id":"https://openalex.org/I70983195","display_name":"Syracuse University","ror":"https://ror.org/025r5qe02","country_code":"US","type":"education","lineage":["https://openalex.org/I70983195"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rudolph","raw_affiliation_strings":["School of Computer and Information Science, Syracuse University, Syracuse, NY, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Computer and Information Science, Syracuse University, Syracuse, NY, USA","institution_ids":["https://openalex.org/I70983195"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.12201154,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"C-29","issue":"11","first_page":"1025","last_page":"1029"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9962999820709229,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13293","display_name":"Engineering and Test Systems","score":0.9918000102043152,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/function","display_name":"Function (biology)","score":0.6033002138137817},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5997722148895264},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.5728753805160522},{"id":"https://openalex.org/keywords/mode","display_name":"Mode (computer interface)","score":0.5711292624473572},{"id":"https://openalex.org/keywords/dual","display_name":"Dual (grammatical number)","score":0.537950336933136},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4995715618133545},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4753284752368927},{"id":"https://openalex.org/keywords/dual-function","display_name":"Dual function","score":0.44723019003868103},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.36303627490997314}],"concepts":[{"id":"https://openalex.org/C14036430","wikidata":"https://www.wikidata.org/wiki/Q3736076","display_name":"Function (biology)","level":2,"score":0.6033002138137817},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5997722148895264},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.5728753805160522},{"id":"https://openalex.org/C48677424","wikidata":"https://www.wikidata.org/wiki/Q6888088","display_name":"Mode (computer interface)","level":2,"score":0.5711292624473572},{"id":"https://openalex.org/C2780980858","wikidata":"https://www.wikidata.org/wiki/Q110022","display_name":"Dual (grammatical number)","level":2,"score":0.537950336933136},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4995715618133545},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4753284752368927},{"id":"https://openalex.org/C3019659684","wikidata":"https://www.wikidata.org/wiki/Q2275559","display_name":"Dual function","level":3,"score":0.44723019003868103},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.36303627490997314},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C78458016","wikidata":"https://www.wikidata.org/wiki/Q840400","display_name":"Evolutionary biology","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C121684516","wikidata":"https://www.wikidata.org/wiki/Q7600677","display_name":"Computer graphics (images)","level":1,"score":0.0},{"id":"https://openalex.org/C124952713","wikidata":"https://www.wikidata.org/wiki/Q8242","display_name":"Literature","level":1,"score":0.0},{"id":"https://openalex.org/C2779104521","wikidata":"https://www.wikidata.org/wiki/Q23058469","display_name":"Contouring","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tc.1980.1675500","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1980.1675500","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W240144897","https://openalex.org/W290503896","https://openalex.org/W2017520945","https://openalex.org/W2038539185","https://openalex.org/W2074742825","https://openalex.org/W2182112064","https://openalex.org/W2796880069","https://openalex.org/W3022683117","https://openalex.org/W3194602862"],"related_works":["https://openalex.org/W29481652","https://openalex.org/W4238178324","https://openalex.org/W4248668797","https://openalex.org/W2110968362","https://openalex.org/W3141297747","https://openalex.org/W2106889348","https://openalex.org/W2111485030","https://openalex.org/W4390345338","https://openalex.org/W96064250","https://openalex.org/W4391701205"],"abstract_inverted_index":{"This":[0,47],"correspondence":[1,48],"presents":[2],"a":[3],"oncept":[4],"of":[5,8,17,32,53],"function-independent":[6,75],"testing":[7],"digital":[9],"networks.":[10],"It":[11],"is":[12,23,35],"based":[13],"on":[14],"the":[15,21,29,33,45,51,56],"idea":[16],"dual-mode":[18],"logic":[19],"where":[20],"network":[22,34],"tested":[24,70],"in":[25,37],"one":[26],"mode":[27,42],"while":[28],"normal":[30],"function":[31],"performed":[36],"another":[38],"mode,":[39],"with":[40,44,55,66,71],"neither":[41],"interfering":[43],"other.":[46],"simultaneously":[49],"defines":[50],"structure":[52],"modules":[54],"above":[57],"characteristics":[58],"such":[59],"that":[60],"combinational":[61],"and":[62,73],"sequential":[63],"networks":[64],"built":[65],"them":[67],"can":[68],"be":[69],"two":[72],"six":[74],"tests,":[76],"respectively.":[77]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}