{"id":"https://openalex.org/W2031516162","doi":"https://doi.org/10.1109/tc.1979.1675433","title":"Minimum Parallel Binary Adders with NOR (NAND) Gates","display_name":"Minimum Parallel Binary Adders with NOR (NAND) Gates","publication_year":1979,"publication_date":"1979-09-01","ids":{"openalex":"https://openalex.org/W2031516162","doi":"https://doi.org/10.1109/tc.1979.1675433","mag":"2031516162"},"language":"en","primary_location":{"id":"doi:10.1109/tc.1979.1675433","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1979.1675433","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","0016-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111391866","display_name":"Hung Lai","orcid":null},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]},{"id":"https://openalex.org/I4210119058","display_name":"National Institute for Research and Development in Microtechnologies","ror":"https://ror.org/01rtq8t93","country_code":"RO","type":"facility","lineage":["https://openalex.org/I4210119058"]}],"countries":["RO","US"],"is_corresponding":false,"raw_author_name":"Hung Chi Lai","raw_affiliation_strings":["Microtechnology Corp","Department of Computer Science, University of Illinois, Urbana-Champaign, IL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microtechnology Corp","institution_ids":["https://openalex.org/I4210119058"]},{"raw_affiliation_string":"Department of Computer Science, University of Illinois, Urbana-Champaign, IL, USA","institution_ids":["https://openalex.org/I157725225"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5056448001","display_name":"Muroga","orcid":null},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Muroga","raw_affiliation_strings":["Department of Computer Science, University of Illinois, Urbana-Champaign, IL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Illinois, Urbana-Champaign, IL, USA","institution_ids":["https://openalex.org/I157725225"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.1939,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.78638544,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"C-28","issue":"9","first_page":"648","last_page":"659"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10682","display_name":"Quantum Computing Algorithms and Architecture","score":0.9879000186920166,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.9362578988075256},{"id":"https://openalex.org/keywords/carry-save-adder","display_name":"Carry-save adder","score":0.6378515958786011},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.6299796104431152},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5643296837806702},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.548622727394104},{"id":"https://openalex.org/keywords/nand-logic","display_name":"NAND logic","score":0.5263323187828064},{"id":"https://openalex.org/keywords/serial-binary-adder","display_name":"Serial binary adder","score":0.514284074306488},{"id":"https://openalex.org/keywords/cascade","display_name":"Cascade","score":0.5050001740455627},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.47886893153190613},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.4510105550289154},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3628386855125427},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.29825282096862793},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.07558810710906982}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.9362578988075256},{"id":"https://openalex.org/C3227080","wikidata":"https://www.wikidata.org/wiki/Q5046770","display_name":"Carry-save adder","level":4,"score":0.6378515958786011},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.6299796104431152},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5643296837806702},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.548622727394104},{"id":"https://openalex.org/C7234692","wikidata":"https://www.wikidata.org/wiki/Q4116068","display_name":"NAND logic","level":4,"score":0.5263323187828064},{"id":"https://openalex.org/C116206932","wikidata":"https://www.wikidata.org/wiki/Q7454686","display_name":"Serial binary adder","level":4,"score":0.514284074306488},{"id":"https://openalex.org/C34146451","wikidata":"https://www.wikidata.org/wiki/Q5048094","display_name":"Cascade","level":2,"score":0.5050001740455627},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.47886893153190613},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.4510105550289154},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3628386855125427},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.29825282096862793},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.07558810710906982},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0},{"id":"https://openalex.org/C42360764","wikidata":"https://www.wikidata.org/wiki/Q83588","display_name":"Chemical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tc.1979.1675433","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1979.1675433","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","0016-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W837381191","https://openalex.org/W1662824729","https://openalex.org/W1964930576","https://openalex.org/W1976034845","https://openalex.org/W2005045860","https://openalex.org/W2024452488","https://openalex.org/W2041576251","https://openalex.org/W2052363354","https://openalex.org/W2061346481","https://openalex.org/W2085126740","https://openalex.org/W2153484041","https://openalex.org/W2169700803","https://openalex.org/W2269105708"],"related_works":["https://openalex.org/W2364181090","https://openalex.org/W4299002946","https://openalex.org/W2950518102","https://openalex.org/W2516396101","https://openalex.org/W2953746839","https://openalex.org/W2370097872","https://openalex.org/W2112595260","https://openalex.org/W4295540194","https://openalex.org/W1993041309","https://openalex.org/W2064215635"],"abstract_inverted_index":{"Parallel":[0],"binary":[1],"adders":[2,46,65,82,95,110,123,137,151],"of":[3,16,26,29,38,51,61,87,93,128],"n":[4],"bits":[5],"long":[6],"in":[7,21,145],"single-rail":[8],"input":[9],"logic":[10,102],"which":[11,83],"have":[12,66,124],"a":[13,49,85],"minimum":[14,126],"number":[15,28,127],"NOR":[17,30,141],"gates":[18,31,68,154],"are":[19,84,96,106,130,138,148],"derived":[20],"this":[22,146],"paper.":[23],"The":[24],"minimality":[25],"the":[27,45,78,100,125,143],"is":[32,42],"proved":[33,43],"for":[34],"an":[35],"arbitrary":[36],"value":[37],"n.":[39],"Also,":[40],"it":[41],"that":[44,55],"must":[47],"be":[48],"cascade":[50,86],"basic":[52,62],"modules":[53],"and":[54,69,114],"there":[56],"exist":[57],"many":[58,107],"different":[59],"types":[60],"modules.":[63],"These":[64],"fewer":[67,75],"shorter":[70],"net":[71,118],"gate":[72,119],"delays":[73,120],"(or":[74],"connections)":[76],"than":[77],"widely":[79],"used":[80],"carry-ripple":[81],"one-bit":[88],"full":[89],"adders.":[90],"Design":[91],"procedures":[92],"such":[94],"described,":[97],"based":[98],"on":[99],"integer-programming":[101],"design":[103],"method.":[104],"There":[105],"solutions":[108],"but":[109],"with":[111,116,140,152],"few":[112,117],"connections":[113],"those":[115],"(all":[121],"these":[122,136],"gates)":[129],"shown":[131],"as":[132],"important":[133],"examples.":[134],"Altbough":[135],"designed":[139],"gates,":[142],"results":[144],"paper":[147],"applicable":[149],"to":[150],"NAND":[153],"by":[155],"duality":[156],"conversion.":[157]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}