{"id":"https://openalex.org/W2054206858","doi":"https://doi.org/10.1109/tc.1979.1675428","title":"Logic Design of Programmable Logic Arrays","display_name":"Logic Design of Programmable Logic Arrays","publication_year":1979,"publication_date":"1979-09-01","ids":{"openalex":"https://openalex.org/W2054206858","doi":"https://doi.org/10.1109/tc.1979.1675428","mag":"2054206858"},"language":"en","primary_location":{"id":"doi:10.1109/tc.1979.1675428","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1979.1675428","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5097146304","display_name":"Kambayashi","orcid":null},"institutions":[{"id":"https://openalex.org/I5023651","display_name":"McGill University","ror":"https://ror.org/01pxwe438","country_code":"CA","type":"education","lineage":["https://openalex.org/I5023651"]},{"id":"https://openalex.org/I22299242","display_name":"Kyoto University","ror":"https://ror.org/02kpeqv85","country_code":"JP","type":"education","lineage":["https://openalex.org/I22299242"]}],"countries":["CA","JP"],"is_corresponding":true,"raw_author_name":"Kambayashi","raw_affiliation_strings":["School of Computer Science, McGill University","School of Computer Science, McGill University, Montreal, QUE, Canada","Department of Information Science, Kyoto University, Kyoto, Japan"],"affiliations":[{"raw_affiliation_string":"School of Computer Science, McGill University","institution_ids":["https://openalex.org/I5023651"]},{"raw_affiliation_string":"School of Computer Science, McGill University, Montreal, QUE, Canada","institution_ids":["https://openalex.org/I5023651"]},{"raw_affiliation_string":"Department of Information Science, Kyoto University, Kyoto, Japan","institution_ids":["https://openalex.org/I22299242"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5097146304"],"corresponding_institution_ids":["https://openalex.org/I22299242","https://openalex.org/I5023651"],"apc_list":null,"apc_paid":null,"fwci":3.5699,"has_fulltext":false,"cited_by_count":56,"citation_normalized_percentile":{"value":0.92840209,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":91,"max":98},"biblio":{"volume":"C-28","issue":"9","first_page":"609","last_page":"617"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5818447470664978},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5630415081977844},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5620675683021545},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.560754656791687},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5496361255645752},{"id":"https://openalex.org/keywords/realization","display_name":"Realization (probability)","score":0.524647057056427},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.5095100998878479},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.4882242977619171},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.47888439893722534},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.45159363746643066},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4269687533378601},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4160327911376953},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.4019913077354431},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.36359238624572754},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.35743477940559387},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.34146648645401},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.28587499260902405},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.11568272113800049},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09068158268928528}],"concepts":[{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5818447470664978},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5630415081977844},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5620675683021545},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.560754656791687},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5496361255645752},{"id":"https://openalex.org/C2781089630","wikidata":"https://www.wikidata.org/wiki/Q21856745","display_name":"Realization (probability)","level":2,"score":0.524647057056427},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.5095100998878479},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.4882242977619171},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.47888439893722534},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.45159363746643066},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4269687533378601},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4160327911376953},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.4019913077354431},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.36359238624572754},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.35743477940559387},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.34146648645401},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.28587499260902405},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.11568272113800049},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09068158268928528},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tc.1979.1675428","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1979.1675428","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2031784867","https://openalex.org/W2048715683","https://openalex.org/W2065966163","https://openalex.org/W2069067423","https://openalex.org/W6663329607"],"related_works":["https://openalex.org/W2994343469","https://openalex.org/W3105918491","https://openalex.org/W2102777336","https://openalex.org/W2789662562","https://openalex.org/W1905312773","https://openalex.org/W2526300902","https://openalex.org/W2525933112","https://openalex.org/W2139569078","https://openalex.org/W4252227487","https://openalex.org/W2170504327"],"abstract_inverted_index":{"Compared":[0],"with":[1,39,50],"random":[2,130],"logic":[3,30,48,131],"circuits,":[4],"memory-type":[5],"circuits":[6,178],"are":[7,90],"more":[8],"suitable":[9,45],"for":[10,46,190],"LSI":[11],"realization":[12],"since":[13],"their":[14],"iterated":[15],"structure":[16],"of":[17,60,63,73,82,88,95,99,102,116,119,142,147,164,170,177],"identical":[18],"cells":[19],"results":[20],"in":[21,67,107,122,128,180],"higher":[22,26],"transistor":[23],"density":[24],"and":[25,42,84,144],"yield.":[27],"A":[28],"programmable":[29,40],"array":[31],"(PLA)":[32],"is":[33,44,65,76,104,126,135],"a":[34,57,74,123,136,152,191],"read":[35],"only":[36],"memory":[37],"(ROM)":[38],"addresses":[41],"it":[43],"realizing":[47],"functions":[49],"many":[51,68],"unspecified":[52],"input":[53,64],"combinations.":[54],"For":[55],"such":[56],"function,":[58],"reduction":[59,98,115],"the":[61,71,80,85,93,97,100,111,114,117,140,145,156,162,168,175,181,187],"number":[62,81,94,101,118,141,146,163,169,176],"possible":[66],"cases.":[69],"Since":[70,133],"cost":[72],"PLA":[75,108],"mainly":[77],"determined":[78],"by":[79,92,155],"pins":[83],"chip,":[86],"both":[87],"which":[89],"affected":[91],"inputs,":[96],"inputs":[103,143],"very":[105],"important":[106,127],"design.":[109],"On":[110],"other":[112],"hand,":[113],"product":[120,148,171],"terms":[121],"sum-of-product":[124],"expression":[125],"conventional":[129],"synthesis.":[132],"there":[134],"tradeoff":[137],"problem":[138],"between":[139],"terms,":[149,172],"we":[150],"give":[151],"design":[153],"procedure":[154],"following":[157],"preference":[158],"order:":[159],"1)":[160],"minimizing":[161,167,174],"pins,":[165],"2)":[166],"3)":[173],"used":[179],"PLA.":[182],"These":[183],"factors":[184],"also":[185],"determine":[186],"area":[188],"required":[189],"chip.":[192]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":3},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":2},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":4}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}