{"id":"https://openalex.org/W2034196789","doi":"https://doi.org/10.1109/tc.1977.1674858","title":"ULM Implicants for Minimization of Univers Logic Module Circuits","display_name":"ULM Implicants for Minimization of Univers Logic Module Circuits","publication_year":1977,"publication_date":"1977-05-01","ids":{"openalex":"https://openalex.org/W2034196789","doi":"https://doi.org/10.1109/tc.1977.1674858","mag":"2034196789"},"language":"en","primary_location":{"id":"doi:10.1109/tc.1977.1674858","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1977.1674858","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5097907681","display_name":"Voith","orcid":null},"institutions":[{"id":"https://openalex.org/I90871651","display_name":"University of Toledo","ror":"https://ror.org/01pbdzh19","country_code":"US","type":"education","lineage":["https://openalex.org/I90871651"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Voith","raw_affiliation_strings":["University of Toledo"],"affiliations":[{"raw_affiliation_string":"University of Toledo","institution_ids":["https://openalex.org/I90871651"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5097907681"],"corresponding_institution_ids":["https://openalex.org/I90871651"],"apc_list":null,"apc_paid":null,"fwci":1.2414,"has_fulltext":false,"cited_by_count":17,"citation_normalized_percentile":{"value":0.79466364,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"C-26","issue":"5","first_page":"417","last_page":"424"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9936000108718872,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/implicant","display_name":"Implicant","score":0.6753966808319092},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.6345629692077637},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.631673276424408},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.5468699932098389},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.5349812507629395},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5080142021179199},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5029777884483337},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4955204725265503},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.47295209765434265},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.38559088110923767},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2576789855957031},{"id":"https://openalex.org/keywords/boolean-function","display_name":"Boolean function","score":0.22610893845558167},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.12081965804100037},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.12004649639129639},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10049623250961304},{"id":"https://openalex.org/keywords/boolean-expression","display_name":"Boolean expression","score":0.05956384539604187}],"concepts":[{"id":"https://openalex.org/C102487863","wikidata":"https://www.wikidata.org/wiki/Q1291626","display_name":"Implicant","level":4,"score":0.6753966808319092},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.6345629692077637},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.631673276424408},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.5468699932098389},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.5349812507629395},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5080142021179199},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5029777884483337},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4955204725265503},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.47295209765434265},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.38559088110923767},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2576789855957031},{"id":"https://openalex.org/C187455244","wikidata":"https://www.wikidata.org/wiki/Q942353","display_name":"Boolean function","level":2,"score":0.22610893845558167},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.12081965804100037},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.12004649639129639},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10049623250961304},{"id":"https://openalex.org/C158465420","wikidata":"https://www.wikidata.org/wiki/Q1979515","display_name":"Boolean expression","level":3,"score":0.05956384539604187}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tc.1977.1674858","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1977.1674858","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1604702710","https://openalex.org/W1972880795","https://openalex.org/W1997420068","https://openalex.org/W1997746047","https://openalex.org/W2025264497","https://openalex.org/W2031401570","https://openalex.org/W2044649285","https://openalex.org/W2061734844","https://openalex.org/W2079951723","https://openalex.org/W2089860941","https://openalex.org/W2145408899","https://openalex.org/W2156028311","https://openalex.org/W2183687117"],"related_works":["https://openalex.org/W4210889883","https://openalex.org/W2098878557","https://openalex.org/W4235895663","https://openalex.org/W2746929098","https://openalex.org/W2386022279","https://openalex.org/W2101877870","https://openalex.org/W2000383684","https://openalex.org/W4296473373","https://openalex.org/W1966764473","https://openalex.org/W2059422871"],"abstract_inverted_index":{"In":[0],"this":[1],"paper":[2],"a":[3,42,49],"method":[4,52],"is":[5,22,53,66],"developed":[6,54],"for":[7,55],"circuit":[8],"minimization":[9],"using":[10,25],"the":[11,45,56,62],"universal":[12],"logic":[13],"modules":[14],"(ULM's)":[15],"of":[16,28,41],"Yau":[17],"and":[18,58],"Tang.":[19],"This":[20],"objective":[21],"obtained":[23],"by":[24],"an":[26,59],"extension":[27,60],"prime":[29],"implicants":[30],"termed":[31],"ULM":[32,35],"implicants.":[33],"Each":[34],"implicant":[36],"implies":[37],"one":[38],"possible":[39],"saving":[40],"module":[43],"in":[44],"tree":[46],"structure":[47],"implementing":[48],"function.":[50],"The":[51],"ULM(l)":[57],"to":[61],"higher":[63],"order":[64],"ULM(p)":[65],"discussed.":[67]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
