{"id":"https://openalex.org/W2135651802","doi":"https://doi.org/10.1109/tc.1976.5009256","title":"Self-Synchronization of Asynchronous Sequential Circuits Employing a General Clock Function","display_name":"Self-Synchronization of Asynchronous Sequential Circuits Employing a General Clock Function","publication_year":1976,"publication_date":"1976-03-01","ids":{"openalex":"https://openalex.org/W2135651802","doi":"https://doi.org/10.1109/tc.1976.5009256","mag":"2135651802"},"language":"en","primary_location":{"id":"doi:10.1109/tc.1976.5009256","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1976.5009256","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102810176","display_name":"Jan Huertas","orcid":"https://orcid.org/0000-0003-2607-5214"},"institutions":[{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"J. L. Huertas","raw_affiliation_strings":["Departamento de Electricidad y Electr\u00f3nica, Facultad de Ciencias, Universidad de Sevilla, Sevilla, Spain"],"affiliations":[{"raw_affiliation_string":"Departamento de Electricidad y Electr\u00f3nica, Facultad de Ciencias, Universidad de Sevilla, Sevilla, Spain","institution_ids":["https://openalex.org/I79238269"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108074864","display_name":"I. Jos\u00e9","orcid":null},"institutions":[{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"J. I. Acha","raw_affiliation_strings":["Departamento de Electricidad y Electr\u00f3nica, Facultad de Ciencias, Universidad de Sevilla, Sevilla, Spain"],"affiliations":[{"raw_affiliation_string":"Departamento de Electricidad y Electr\u00f3nica, Facultad de Ciencias, Universidad de Sevilla, Sevilla, Spain","institution_ids":["https://openalex.org/I79238269"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5102810176"],"corresponding_institution_ids":["https://openalex.org/I79238269"],"apc_list":null,"apc_paid":null,"fwci":1.2632,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.819258,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"C-25","issue":"3","first_page":"297","last_page":"300"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.9947999715805054,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10682","display_name":"Quantum Computing Algorithms and Architecture","score":0.9909999966621399,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.8246557712554932},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.733749508857727},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.6879684925079346},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.6652334332466125},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.5752883553504944},{"id":"https://openalex.org/keywords/asynchronous-system","display_name":"Asynchronous system","score":0.5700775384902954},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5641939043998718},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.5624797344207764},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.4944028854370117},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.47007137537002563},{"id":"https://openalex.org/keywords/function","display_name":"Function (biology)","score":0.4681045711040497},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.4555330276489258},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.4145287275314331},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.31545212864875793},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.18623220920562744},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.10961171984672546},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.10785269737243652},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10601314902305603},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.08234411478042603}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.8246557712554932},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.733749508857727},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.6879684925079346},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.6652334332466125},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.5752883553504944},{"id":"https://openalex.org/C7923308","wikidata":"https://www.wikidata.org/wiki/Q4812211","display_name":"Asynchronous system","level":5,"score":0.5700775384902954},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5641939043998718},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.5624797344207764},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.4944028854370117},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.47007137537002563},{"id":"https://openalex.org/C14036430","wikidata":"https://www.wikidata.org/wiki/Q3736076","display_name":"Function (biology)","level":2,"score":0.4681045711040497},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.4555330276489258},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.4145287275314331},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.31545212864875793},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.18623220920562744},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.10961171984672546},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.10785269737243652},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10601314902305603},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.08234411478042603},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C78458016","wikidata":"https://www.wikidata.org/wiki/Q840400","display_name":"Evolutionary biology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tc.1976.5009256","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1976.5009256","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W151521611","https://openalex.org/W1979192072","https://openalex.org/W2005620514","https://openalex.org/W2021934043","https://openalex.org/W2033724727","https://openalex.org/W2062857500","https://openalex.org/W2317462728"],"related_works":["https://openalex.org/W2384756109","https://openalex.org/W4312516786","https://openalex.org/W364924225","https://openalex.org/W2237508561","https://openalex.org/W1993985975","https://openalex.org/W142020038","https://openalex.org/W2377749234","https://openalex.org/W2078264798","https://openalex.org/W174989240","https://openalex.org/W1731143506"],"abstract_inverted_index":{"A":[0,38],"self-synchronization":[1],"model":[2],"is":[3,6,22,32,45],"developed.":[4],"It":[5],"based":[7],"on":[8,16],"a":[9],"general":[10],"clock":[11],"function":[12,21],"which":[13,41],"depends":[14],"only":[15],"the":[17,25,35,50,67],"state":[18],"variables.":[19],"This":[20],"associated":[23],"with":[24],"flip-flop":[26],"type":[27],"to":[28,60],"be":[29,57],"used":[30],"and":[31,70],"independent":[33],"of":[34,66],"flow":[36],"table.":[37],"modular":[39],"implementation":[40],"uses":[42],"integrated":[43],"circuits":[44,62],"obtained.":[46],"With":[47],"this":[48],"technique,":[49],"synthesis":[51],"procedures":[52],"for":[53],"synchronous":[54],"machines":[55],"can":[56],"directly":[58],"applicable":[59],"asynchronous":[61],"without":[63],"taking":[64],"care":[65],"critical":[68],"races":[69],"essential":[71],"hazards.":[72]},"counts_by_year":[{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}