{"id":"https://openalex.org/W1972456335","doi":"https://doi.org/10.1109/tc.1976.5009199","title":"Testable Sequential Cellular Arrays","display_name":"Testable Sequential Cellular Arrays","publication_year":1976,"publication_date":"1976-01-01","ids":{"openalex":"https://openalex.org/W1972456335","doi":"https://doi.org/10.1109/tc.1976.5009199","mag":"1972456335"},"language":"en","primary_location":{"id":"doi:10.1109/tc.1976.5009199","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1976.5009199","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","0016-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5113528397","display_name":"Chia-Hsiaing Sung","orcid":null},"institutions":[{"id":"https://openalex.org/I142740786","display_name":"University of Louisville","ror":"https://ror.org/01ckdn478","country_code":"US","type":"education","lineage":["https://openalex.org/I142740786"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Chia-Hsiaing Sung","raw_affiliation_strings":["Department of Applied Mathematics and Computer Science and the Engineering Computing Laboratory, University of Louisville, Louisville, KY, USA","Department of Applied Mathematics and Computer Science and the Engineering Computing Laboratory, University of Louisville, Louisville, KY 40208"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Applied Mathematics and Computer Science and the Engineering Computing Laboratory, University of Louisville, Louisville, KY, USA","institution_ids":["https://openalex.org/I142740786"]},{"raw_affiliation_string":"Department of Applied Mathematics and Computer Science and the Engineering Computing Laboratory, University of Louisville, Louisville, KY 40208","institution_ids":["https://openalex.org/I142740786"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5113528397"],"corresponding_institution_ids":["https://openalex.org/I142740786"],"apc_list":null,"apc_paid":null,"fwci":0.5614,"has_fulltext":false,"cited_by_count":25,"citation_normalized_percentile":{"value":0.59301746,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":95,"max":97},"biblio":{"volume":"C-25","issue":"1","first_page":"11","last_page":"18"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12162","display_name":"Cellular Automata and Applications","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12162","display_name":"Cellular Automata and Applications","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.994700014591217,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6124898195266724},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.5164332985877991},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.5052333474159241},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4376988708972931},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.40611976385116577},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.37786412239074707},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3764001727104187},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3293015956878662},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.20657265186309814},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2016323208808899},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.17991453409194946},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.0765952467918396}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6124898195266724},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.5164332985877991},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.5052333474159241},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4376988708972931},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.40611976385116577},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.37786412239074707},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3764001727104187},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3293015956878662},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.20657265186309814},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2016323208808899},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.17991453409194946},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.0765952467918396}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tc.1976.5009199","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1976.5009199","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","0016-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.4000000059604645,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1969911580","https://openalex.org/W1981054579","https://openalex.org/W1993690617","https://openalex.org/W1995373767","https://openalex.org/W2005277028","https://openalex.org/W2017391294","https://openalex.org/W2065550034","https://openalex.org/W2067198006","https://openalex.org/W2071210234","https://openalex.org/W2085979004","https://openalex.org/W2086312453","https://openalex.org/W2089338649","https://openalex.org/W2133430959","https://openalex.org/W2135499091","https://openalex.org/W2138671757","https://openalex.org/W2147573597","https://openalex.org/W2293212274","https://openalex.org/W2532227279","https://openalex.org/W2535165249"],"related_works":["https://openalex.org/W2159970201","https://openalex.org/W240144897","https://openalex.org/W2991418621","https://openalex.org/W1912101345","https://openalex.org/W2132796854","https://openalex.org/W1870892037","https://openalex.org/W1733224658","https://openalex.org/W2594283002","https://openalex.org/W2990914696","https://openalex.org/W2008343180"],"abstract_inverted_index":{"The":[0],"progress":[1],"of":[2,13,28,48,64],"semiconductor":[3],"technology":[4],"has":[5,84],"been":[6],"a":[7,21,29,49],"dominant":[8],"factor":[9],"on":[10],"the":[11,26,36,42,46,53,62],"use":[12],"cellular":[14,30,67],"arrays":[15,68,80],"in":[16,25,52],"digital":[17],"computer":[18],"design.":[19],"When":[20],"subsystem":[22,37],"is":[23,33],"implemented":[24],"form":[27],"array,":[31],"it":[32],"important":[34],"that":[35],"can":[38,72],"be":[39,73],"tested":[40],"at":[41],"array":[43],"terminals":[44],"for":[45,61],"presence":[47],"faulty":[50],"cell":[51,83],"array.":[54],"In":[55],"this":[56],"paper":[57],"some":[58,85],"sufficient":[59],"conditions":[60],"testability":[63],"two-dimensional":[65],"sequential":[66],"are":[69],"derived.":[70],"These":[71],"either":[74],"unilaterally":[75],"interconnected":[76,79],"or":[77],"bilaterally":[78],"where":[81],"each":[82],"storage":[86],"elements":[87],"and":[88],"logic":[89],"circuits.":[90]},"counts_by_year":[{"year":2021,"cited_by_count":3}],"updated_date":"2026-07-22T07:51:19.307946","created_date":"2025-10-10T00:00:00"}