{"id":"https://openalex.org/W1981071969","doi":"https://doi.org/10.1109/tc.1976.1674722","title":"Logic Design Using EFL Structures","display_name":"Logic Design Using EFL Structures","publication_year":1976,"publication_date":"1976-09-01","ids":{"openalex":"https://openalex.org/W1981071969","doi":"https://doi.org/10.1109/tc.1976.1674722","mag":"1981071969"},"language":"en","primary_location":{"id":"doi:10.1109/tc.1976.1674722","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1976.1674722","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030845241","display_name":"Elmasry","orcid":null},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Elmasry","raw_affiliation_strings":["The Department of Electrical Engineering, University of Waterloo, Waterloo, ONT, Canada","Dept. of Electrical Eng. University of Waterloo"],"affiliations":[{"raw_affiliation_string":"The Department of Electrical Engineering, University of Waterloo, Waterloo, ONT, Canada","institution_ids":["https://openalex.org/I151746483"]},{"raw_affiliation_string":"Dept. of Electrical Eng. University of Waterloo","institution_ids":["https://openalex.org/I151746483"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5030845241"],"corresponding_institution_ids":["https://openalex.org/I151746483"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.11965812,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"C-25","issue":"9","first_page":"952","last_page":"956"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/emitter-coupled-logic","display_name":"Emitter-coupled logic","score":0.8630432486534119},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6364614367485046},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.6285258531570435},{"id":"https://openalex.org/keywords/realization","display_name":"Realization (probability)","score":0.5670075416564941},{"id":"https://openalex.org/keywords/resistor\u2013transistor-logic","display_name":"Resistor\u2013transistor logic","score":0.5668417811393738},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5376092195510864},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.53421550989151},{"id":"https://openalex.org/keywords/diode\u2013transistor-logic","display_name":"Diode\u2013transistor logic","score":0.5175294280052185},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.46137580275535583},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.44940656423568726},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.4486187696456909},{"id":"https://openalex.org/keywords/function","display_name":"Function (biology)","score":0.43521901965141296},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.33125177025794983},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3015327453613281},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.229121595621109},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2007204294204712},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.18775230646133423},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.17896345257759094},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11461719870567322}],"concepts":[{"id":"https://openalex.org/C11644886","wikidata":"https://www.wikidata.org/wiki/Q173552","display_name":"Emitter-coupled logic","level":5,"score":0.8630432486534119},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6364614367485046},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.6285258531570435},{"id":"https://openalex.org/C2781089630","wikidata":"https://www.wikidata.org/wiki/Q21856745","display_name":"Realization (probability)","level":2,"score":0.5670075416564941},{"id":"https://openalex.org/C180405849","wikidata":"https://www.wikidata.org/wiki/Q173464","display_name":"Resistor\u2013transistor logic","level":5,"score":0.5668417811393738},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5376092195510864},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.53421550989151},{"id":"https://openalex.org/C118759142","wikidata":"https://www.wikidata.org/wiki/Q173475","display_name":"Diode\u2013transistor logic","level":5,"score":0.5175294280052185},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.46137580275535583},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.44940656423568726},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.4486187696456909},{"id":"https://openalex.org/C14036430","wikidata":"https://www.wikidata.org/wiki/Q3736076","display_name":"Function (biology)","level":2,"score":0.43521901965141296},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.33125177025794983},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3015327453613281},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.229121595621109},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2007204294204712},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.18775230646133423},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.17896345257759094},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11461719870567322},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C78458016","wikidata":"https://www.wikidata.org/wiki/Q840400","display_name":"Evolutionary biology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tc.1976.1674722","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1976.1674722","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1538324362","https://openalex.org/W1983370375","https://openalex.org/W2005277028","https://openalex.org/W2017391294","https://openalex.org/W2031401570","https://openalex.org/W2052347134","https://openalex.org/W2078249298","https://openalex.org/W2079477087","https://openalex.org/W2081309480","https://openalex.org/W2089388764","https://openalex.org/W2089860941","https://openalex.org/W2097085318","https://openalex.org/W2102506473","https://openalex.org/W2132641857","https://openalex.org/W2136430947","https://openalex.org/W2146049589","https://openalex.org/W2153294885","https://openalex.org/W2156028311","https://openalex.org/W2541515605","https://openalex.org/W3216306682"],"related_works":["https://openalex.org/W2096007426","https://openalex.org/W2021357106","https://openalex.org/W2017528947","https://openalex.org/W1983370375","https://openalex.org/W1513412524","https://openalex.org/W2079477087","https://openalex.org/W2058822291","https://openalex.org/W2082591327","https://openalex.org/W2167525841","https://openalex.org/W2163914505"],"abstract_inverted_index":{"The":[0,15],"emitter":[1],"function":[2],"iogic":[3],"(EFL)":[4],"structure":[5,16,51],"is":[6,17,66],"a":[7,18,41,62],"bipolar":[8],"integratable":[9],"circuit":[10],"suitable":[11],"for":[12],"large-scale-integration":[13],"(LSI).":[14],"development":[19],"of":[20,29,56],"current-mode":[21],"logic":[22,31,53,63],"and":[23,37,61],"it":[24],"permits":[25],"the":[26,50],"LSI":[27],"realization":[28],"complex":[30],"functions":[32],"with":[33,68],"similar":[34],"silicon":[35],"area":[36],"power":[38],"dissipation":[39],"to":[40,48],"single":[42],"conventional":[43],"ECL":[44],"gate.":[45],"In":[46],"order":[47],"use":[49],"in":[52],"design,":[54],"some":[55],"its":[57],"properties":[58],"are":[59],"developed":[60],"design":[64],"technique":[65],"given":[67],"examples.":[69]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
