{"id":"https://openalex.org/W2157964739","doi":"https://doi.org/10.1109/tc.1976.1674683","title":"Statistical Analysis of a Differential Threshold Logic Circuit Configuration","display_name":"Statistical Analysis of a Differential Threshold Logic Circuit Configuration","publication_year":1976,"publication_date":"1976-07-01","ids":{"openalex":"https://openalex.org/W2157964739","doi":"https://doi.org/10.1109/tc.1976.1674683","mag":"2157964739"},"language":"en","primary_location":{"id":"doi:10.1109/tc.1976.1674683","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1976.1674683","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5098551091","display_name":"Baugh","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Baugh","raw_affiliation_strings":["Bell Laboratories, Holmdel, NJ, USA"],"affiliations":[{"raw_affiliation_string":"Bell Laboratories, Holmdel, NJ, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5083465526","display_name":"Wooley","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Wooley","raw_affiliation_strings":["Bell Laboratories, Holmdel, NJ, USA"],"affiliations":[{"raw_affiliation_string":"Bell Laboratories, Holmdel, NJ, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5098551091"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.24359795,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"C-25","issue":"7","first_page":"745","last_page":"754"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9932000041007996,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/emitter-coupled-logic","display_name":"Emitter-coupled logic","score":0.7227095365524292},{"id":"https://openalex.org/keywords/resistor\u2013transistor-logic","display_name":"Resistor\u2013transistor logic","score":0.65868079662323},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5993225574493408},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5915160775184631},{"id":"https://openalex.org/keywords/logic-level","display_name":"Logic level","score":0.5607582330703735},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.560462236404419},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.527508556842804},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.48184478282928467},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.48164382576942444},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.45639440417289734},{"id":"https://openalex.org/keywords/diode\u2013transistor-logic","display_name":"Diode\u2013transistor logic","score":0.43629083037376404},{"id":"https://openalex.org/keywords/differential","display_name":"Differential (mechanical device)","score":0.43380579352378845},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4188166856765747},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4103955626487732},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.39256399869918823},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2858317494392395},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.24761304259300232},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.13871029019355774},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12541905045509338},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.10776665806770325},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.077644944190979}],"concepts":[{"id":"https://openalex.org/C11644886","wikidata":"https://www.wikidata.org/wiki/Q173552","display_name":"Emitter-coupled logic","level":5,"score":0.7227095365524292},{"id":"https://openalex.org/C180405849","wikidata":"https://www.wikidata.org/wiki/Q173464","display_name":"Resistor\u2013transistor logic","level":5,"score":0.65868079662323},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5993225574493408},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5915160775184631},{"id":"https://openalex.org/C146569638","wikidata":"https://www.wikidata.org/wiki/Q173378","display_name":"Logic level","level":3,"score":0.5607582330703735},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.560462236404419},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.527508556842804},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.48184478282928467},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.48164382576942444},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.45639440417289734},{"id":"https://openalex.org/C118759142","wikidata":"https://www.wikidata.org/wiki/Q173475","display_name":"Diode\u2013transistor logic","level":5,"score":0.43629083037376404},{"id":"https://openalex.org/C93226319","wikidata":"https://www.wikidata.org/wiki/Q193137","display_name":"Differential (mechanical device)","level":2,"score":0.43380579352378845},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4188166856765747},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4103955626487732},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.39256399869918823},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2858317494392395},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.24761304259300232},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.13871029019355774},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12541905045509338},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.10776665806770325},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.077644944190979},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tc.1976.1674683","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1976.1674683","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.6899999976158142}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W2083376242","https://openalex.org/W2101400068","https://openalex.org/W2295866677"],"related_works":["https://openalex.org/W2108396794","https://openalex.org/W2139554797","https://openalex.org/W2030233713","https://openalex.org/W2131757811","https://openalex.org/W2350960814","https://openalex.org/W2140909357","https://openalex.org/W2082591327","https://openalex.org/W2049889603","https://openalex.org/W1513412524","https://openalex.org/W1981243998"],"abstract_inverted_index":{"A":[0],"differential":[1],"current-switching":[2],"circuit":[3],"configuration":[4,18,22],"is":[5,19,23,40],"proposed":[6],"for":[7,25],"implementing":[8],"threshold":[9],"logic,":[10],"and":[11],"a":[12,37],"first-order":[13],"statistical":[14],"analysis":[15],"of":[16],"the":[17],"described.":[20],"The":[21],"intended":[24],"use":[26],"within":[27],"functional":[28],"digital":[29],"integrated":[30],"circuits.":[31],"It":[32],"can":[33],"be":[34],"realized":[35],"in":[36],"form":[38],"that":[39],"fully":[41],"compatible":[42],"with":[43],"conventional":[44],"emitter-coupled":[45],"logic":[46],"(ECL).":[47]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}