{"id":"https://openalex.org/W2026731014","doi":"https://doi.org/10.1109/tc.1976.1674663","title":"A Nine-Valued Circuit Model for Test Generation","display_name":"A Nine-Valued Circuit Model for Test Generation","publication_year":1976,"publication_date":"1976-06-01","ids":{"openalex":"https://openalex.org/W2026731014","doi":"https://doi.org/10.1109/tc.1976.1674663","mag":"2026731014"},"language":"en","primary_location":{"id":"doi:10.1109/tc.1976.1674663","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1976.1674663","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5097455518","display_name":"Muth","orcid":null},"institutions":[{"id":"https://openalex.org/I4210166982","display_name":"ABB (Germany)","ror":"https://ror.org/05yeg2858","country_code":"DE","type":"company","lineage":["https://openalex.org/I4210166982","https://openalex.org/I885143765"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Muth","raw_affiliation_strings":["Brown, Boveri, and Cie AG","Institute for Information Processing, University of Karlsruhe, Karlsruhe, Germany","Brown Boveri and Cie, AG, Mannheim, Germany"],"affiliations":[{"raw_affiliation_string":"Brown, Boveri, and Cie AG","institution_ids":[]},{"raw_affiliation_string":"Institute for Information Processing, University of Karlsruhe, Karlsruhe, Germany","institution_ids":[]},{"raw_affiliation_string":"Brown Boveri and Cie, AG, Mannheim, Germany","institution_ids":["https://openalex.org/I4210166982"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5097455518"],"corresponding_institution_ids":["https://openalex.org/I4210166982"],"apc_list":null,"apc_paid":null,"fwci":2.185,"has_fulltext":false,"cited_by_count":172,"citation_normalized_percentile":{"value":0.85780347,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"C-25","issue":"6","first_page":"630","last_page":"636"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":0.9850000143051147,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.982200026512146,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.7129495739936829},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.6341179609298706},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.579259991645813},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5656898021697998},{"id":"https://openalex.org/keywords/test","display_name":"Test (biology)","score":0.5564050078392029},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.522911012172699},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.432373046875},{"id":"https://openalex.org/keywords/fault-model","display_name":"Fault model","score":0.42797982692718506},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.35195401310920715},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.24948722124099731},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10506114363670349}],"concepts":[{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.7129495739936829},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.6341179609298706},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.579259991645813},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5656898021697998},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.5564050078392029},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.522911012172699},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.432373046875},{"id":"https://openalex.org/C167391956","wikidata":"https://www.wikidata.org/wiki/Q1401211","display_name":"Fault model","level":3,"score":0.42797982692718506},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.35195401310920715},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.24948722124099731},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10506114363670349},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tc.1976.1674663","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1976.1674663","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2030918492","https://openalex.org/W2087047691","https://openalex.org/W2120688461","https://openalex.org/W2989460830","https://openalex.org/W6770870115"],"related_works":["https://openalex.org/W2117873690","https://openalex.org/W3141249762","https://openalex.org/W1518694365","https://openalex.org/W2137555930","https://openalex.org/W2147400189","https://openalex.org/W2568949342","https://openalex.org/W2340957901","https://openalex.org/W1555400249","https://openalex.org/W2031110496","https://openalex.org/W2157154381"],"abstract_inverted_index":{"A":[0],"nine-valued":[1],"circuit":[2],"model":[3,25],"for":[4],"test":[5,26,49,64],"generation":[6],"is":[7],"introduced":[8],"which":[9,31],"takes":[10],"care":[11],"of":[12,17,37,43],"multiple":[13,33],"and":[14,34],"repeated":[15,35],"effects":[16,36],"a":[18,44],"fault":[19],"in":[20],"sequential":[21,45],"circuits.":[22],"Using":[23],"this":[24],"sequences":[27,50],"can":[28],"be":[29],"determined":[30],"allow":[32],"faults":[38],"on":[39],"the":[40,58],"internal":[41],"state":[42],"circuit.":[46],"Thus":[47],"valid":[48],"are":[51],"derived":[52],"where":[53],"other":[54],"known":[55],"procedures,":[56],"like":[57],"D-algorithm,":[59],"do":[60],"not":[61],"find":[62],"any":[63],"although":[65],"one":[66],"exists.":[67]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
