{"id":"https://openalex.org/W2003439414","doi":"https://doi.org/10.1109/tc.1976.1674578","title":"Synchronous and Asynchronous Procedures for the Synthesis of Master-Slave Circuits","display_name":"Synchronous and Asynchronous Procedures for the Synthesis of Master-Slave Circuits","publication_year":1976,"publication_date":"1976-11-01","ids":{"openalex":"https://openalex.org/W2003439414","doi":"https://doi.org/10.1109/tc.1976.1674578","mag":"2003439414"},"language":"en","primary_location":{"id":"doi:10.1109/tc.1976.1674578","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1976.1674578","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","0016-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014360126","display_name":"Frosini","orcid":null},"institutions":[{"id":"https://openalex.org/I122991210","display_name":"Istituto di Scienza e Tecnologie dell'Informazione \"Alessandro Faedo\"","ror":"https://ror.org/05kacka20","country_code":"IT","type":"facility","lineage":["https://openalex.org/I122991210","https://openalex.org/I4210155236"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Frosini","raw_affiliation_strings":["Istituto di Elaborazione della Informazione, Consiglio Nazionale delle Ricerche","Istituto di Elaborazione della Informazione, Consiglio Nationale delle Ricerche, Pisa, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Istituto di Elaborazione della Informazione, Consiglio Nazionale delle Ricerche","institution_ids":["https://openalex.org/I122991210"]},{"raw_affiliation_string":"Istituto di Elaborazione della Informazione, Consiglio Nationale delle Ricerche, Pisa, Italy","institution_ids":["https://openalex.org/I122991210"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5073282029","display_name":"Gerace","orcid":null},"institutions":[{"id":"https://openalex.org/I108290504","display_name":"University of Pisa","ror":"https://ror.org/03ad39j10","country_code":"IT","type":"education","lineage":["https://openalex.org/I108290504"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Gerace","raw_affiliation_strings":["Istituto di Scienze dell'informazione, Universit\u00e0 di Pisa, Pisa, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Istituto di Scienze dell'informazione, Universit\u00e0 di Pisa, Pisa, Italy","institution_ids":["https://openalex.org/I108290504"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.12659762,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"C-25","issue":"11","first_page":"1179","last_page":"1184"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9815000295639038,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9815000295639038,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11283","display_name":"Experimental Learning in Engineering","score":0.9815000295639038,"subfield":{"id":"https://openalex.org/subfields/2214","display_name":"Media Technology"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.9628000259399414,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.8861501812934875},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.7457795143127441},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.733989953994751},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7067133188247681},{"id":"https://openalex.org/keywords/master/slave","display_name":"Master/slave","score":0.6807940602302551},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.46723300218582153},{"id":"https://openalex.org/keywords/synchronizer","display_name":"Synchronizer","score":0.45650842785835266},{"id":"https://openalex.org/keywords/asynchronous-system","display_name":"Asynchronous system","score":0.44646361470222473},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3295101225376129},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.30920475721359253},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.23790377378463745},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2139328122138977},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11905020475387573},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11518263816833496},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.08307051658630371}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.8861501812934875},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.7457795143127441},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.733989953994751},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7067133188247681},{"id":"https://openalex.org/C20454292","wikidata":"https://www.wikidata.org/wiki/Q735523","display_name":"Master/slave","level":2,"score":0.6807940602302551},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.46723300218582153},{"id":"https://openalex.org/C66727535","wikidata":"https://www.wikidata.org/wiki/Q7662199","display_name":"Synchronizer","level":2,"score":0.45650842785835266},{"id":"https://openalex.org/C7923308","wikidata":"https://www.wikidata.org/wiki/Q4812211","display_name":"Asynchronous system","level":5,"score":0.44646361470222473},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3295101225376129},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.30920475721359253},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.23790377378463745},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2139328122138977},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11905020475387573},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11518263816833496},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.08307051658630371},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tc.1976.1674578","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1976.1674578","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","0016-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W151521611","https://openalex.org/W2005130273","https://openalex.org/W2007696147","https://openalex.org/W2013310157","https://openalex.org/W2025725929","https://openalex.org/W2060810175","https://openalex.org/W2089904802","https://openalex.org/W2141148533","https://openalex.org/W2317462728","https://openalex.org/W2542243686","https://openalex.org/W3177082579"],"related_works":["https://openalex.org/W364924225","https://openalex.org/W60393894","https://openalex.org/W2095703739","https://openalex.org/W1993985975","https://openalex.org/W2093992207","https://openalex.org/W2325117947","https://openalex.org/W628161287","https://openalex.org/W158833317","https://openalex.org/W794031490","https://openalex.org/W2349909378"],"abstract_inverted_index":{"The":[0],"synchronous":[1,21,43],"procedure":[2,6,22,34],"and":[3],"the":[4,8,20,32,42,49],"asynchronous":[5,33],"for":[7],"synthesis":[9],"of":[10],"a":[11,25],"master-slave":[12],"circuit":[13,26,51],"are":[14],"examined.":[15],"It":[16],"is":[17,52],"shown":[18],"that":[19],"leads":[23],"to":[24],"operating":[27],"in":[28],"fundamental":[29],"mode,":[30],"while":[31],"can":[35],"be":[36],"performed":[37],"by":[38],"taking":[39],"into":[40],"account":[41],"flow":[44],"table.":[45],"In":[46],"both":[47],"cases":[48],"same":[50],"obtained.":[53]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}