{"id":"https://openalex.org/W2171074326","doi":"https://doi.org/10.1109/tai.2002.1180847","title":"A genetic testing framework for digital integrated circuits","display_name":"A genetic testing framework for digital integrated circuits","publication_year":2003,"publication_date":"2003-06-26","ids":{"openalex":"https://openalex.org/W2171074326","doi":"https://doi.org/10.1109/tai.2002.1180847","mag":"2171074326"},"language":"en","primary_location":{"id":"doi:10.1109/tai.2002.1180847","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tai.2002.1180847","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"14th IEEE International Conference on Tools with Artificial Intelligence, 2002. (ICTAI 2002). Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101888104","display_name":"Xiaoming Yu","orcid":"https://orcid.org/0000-0001-5799-8519"},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xiaoming Yu","raw_affiliation_strings":["Center for Reliable & High-Performance Computing, University of Illinois, Urbana-Champaign, IL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Center for Reliable & High-Performance Computing, University of Illinois, Urbana-Champaign, IL, USA","institution_ids":["https://openalex.org/I157725225"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037661652","display_name":"Alessandro Fin","orcid":null},"institutions":[{"id":"https://openalex.org/I119439378","display_name":"University of Verona","ror":"https://ror.org/039bp8j42","country_code":"IT","type":"education","lineage":["https://openalex.org/I119439378"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"A. Fin","raw_affiliation_strings":["Dipartimento di Informatica, Universit\u00e0 di Verona, Verona, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Informatica, Universit\u00e0 di Verona, Verona, Italy","institution_ids":["https://openalex.org/I119439378"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040302302","display_name":"Franco Fummi","orcid":"https://orcid.org/0000-0002-4404-5791"},"institutions":[{"id":"https://openalex.org/I119439378","display_name":"University of Verona","ror":"https://ror.org/039bp8j42","country_code":"IT","type":"education","lineage":["https://openalex.org/I119439378"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"F. Fummi","raw_affiliation_strings":["Dipartimento di Informatica, Universit\u00e0 di Verona, Verona, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Informatica, Universit\u00e0 di Verona, Verona, Italy","institution_ids":["https://openalex.org/I119439378"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043415886","display_name":"E.M. Rudnick","orcid":null},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"E.M. Rudnick","raw_affiliation_strings":["Center for Reliable & High-Performance Computing, University of Illinois, Urbana-Champaign, IL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Center for Reliable & High-Performance Computing, University of Illinois, Urbana-Champaign, IL, USA","institution_ids":["https://openalex.org/I157725225"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.7432,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.74532186,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"521","last_page":"526"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9718000292778015,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.7286314368247986},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.7102950215339661},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.6920236349105835},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6609577536582947},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.6372929215431213},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.6185833215713501},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.6107602715492249},{"id":"https://openalex.org/keywords/functional-testing","display_name":"Functional testing","score":0.5320006012916565},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5122172236442566},{"id":"https://openalex.org/keywords/test-compression","display_name":"Test compression","score":0.4629673957824707},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.4368763566017151},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.41912710666656494},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.41566282510757446},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.367722749710083},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.35647425055503845},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20041245222091675},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.18382012844085693},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.08132374286651611}],"concepts":[{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.7286314368247986},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.7102950215339661},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.6920236349105835},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6609577536582947},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.6372929215431213},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.6185833215713501},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.6107602715492249},{"id":"https://openalex.org/C80823478","wikidata":"https://www.wikidata.org/wiki/Q4493432","display_name":"Functional testing","level":3,"score":0.5320006012916565},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5122172236442566},{"id":"https://openalex.org/C29652920","wikidata":"https://www.wikidata.org/wiki/Q7705757","display_name":"Test compression","level":4,"score":0.4629673957824707},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.4368763566017151},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.41912710666656494},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.41566282510757446},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.367722749710083},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.35647425055503845},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20041245222091675},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.18382012844085693},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.08132374286651611}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tai.2002.1180847","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tai.2002.1180847","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"14th IEEE International Conference on Tools with Artificial Intelligence, 2002. (ICTAI 2002). Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W1554885925","https://openalex.org/W1594852956","https://openalex.org/W1886859778","https://openalex.org/W1964839541","https://openalex.org/W1986875761","https://openalex.org/W2034263428","https://openalex.org/W2060461359","https://openalex.org/W2109951594","https://openalex.org/W2115649468","https://openalex.org/W2124618076","https://openalex.org/W2130577561","https://openalex.org/W2135931142","https://openalex.org/W2137246866","https://openalex.org/W2145401040","https://openalex.org/W2150360866","https://openalex.org/W2152150600","https://openalex.org/W2168677788","https://openalex.org/W2904250082","https://openalex.org/W3010856131","https://openalex.org/W3023540311","https://openalex.org/W4230587734","https://openalex.org/W4239481074","https://openalex.org/W4245928206","https://openalex.org/W4250962413","https://openalex.org/W4302458519","https://openalex.org/W6684535205"],"related_works":["https://openalex.org/W2107525390","https://openalex.org/W2157191248","https://openalex.org/W2150046587","https://openalex.org/W2142405811","https://openalex.org/W2114980936","https://openalex.org/W2164493372","https://openalex.org/W1594445436","https://openalex.org/W2128920253","https://openalex.org/W2157212570","https://openalex.org/W1595513435"],"abstract_inverted_index":{"In":[0],"order":[1],"to":[2],"reduce":[3],"the":[4,63,66,70,77],"time-to-market":[5],"and":[6,24,39,51,58,75],"simplify":[7],"gate-level":[8,78],"test":[9,17,72],"generation":[10,18,73],"for":[11,22,36,55],"digital":[12],"integrated":[13],"circuits,":[14],"GA-based":[15],"functional":[16,30],"techniques":[19],"are":[20],"proposed":[21],"behavioral":[23],"register":[25,49],"transfer":[26,50],"level":[27],"designs.":[28],"The":[29],"tests":[31],"generated":[32],"can":[33,41],"be":[34,43],"used":[35],"design":[37],"verification,":[38],"they":[40],"also":[42],"reused":[44],"at":[45],"lower":[46],"levels":[47],"(i.e.":[48],"logic":[52],"gate":[53],"levels)":[54],"testability":[56],"analysis":[57],"development.":[59],"Experimental":[60],"results":[61],"demonstrate":[62],"effectiveness":[64],"of":[65],"method":[67],"in":[68],"reducing":[69],"overall":[71],"time":[74],"increasing":[76],"fault":[79],"coverage.":[80]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2015,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}