{"id":"https://openalex.org/W2903991555","doi":"https://doi.org/10.1109/ssd.2018.8570602","title":"On the Design of Nanoscale CMOS Threshold-Logic Adders","display_name":"On the Design of Nanoscale CMOS Threshold-Logic Adders","publication_year":2018,"publication_date":"2018-03-01","ids":{"openalex":"https://openalex.org/W2903991555","doi":"https://doi.org/10.1109/ssd.2018.8570602","mag":"2903991555"},"language":"en","primary_location":{"id":"doi:10.1109/ssd.2018.8570602","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ssd.2018.8570602","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 15th International Multi-Conference on Systems, Signals & Devices (SSD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5015702025","display_name":"Mawahib Hussein Sulieman","orcid":null},"institutions":[{"id":"https://openalex.org/I161913731","display_name":"Al Ain University","ror":"https://ror.org/023abrt21","country_code":"AE","type":"education","lineage":["https://openalex.org/I161913731"]}],"countries":["AE"],"is_corresponding":true,"raw_author_name":"Mawahib Hussein Sulieman","raw_affiliation_strings":["College of Engineering, Al Ain University of Science and Technology, A1 Ain, UAE"],"affiliations":[{"raw_affiliation_string":"College of Engineering, Al Ain University of Science and Technology, A1 Ain, UAE","institution_ids":["https://openalex.org/I161913731"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5049064039","display_name":"Zakaria Fadlalmoula M. Himat","orcid":"https://orcid.org/0000-0001-8505-6270"},"institutions":[{"id":"https://openalex.org/I124866261","display_name":"Al Ghurair University","ror":"https://ror.org/05y8x6h30","country_code":"AE","type":"education","lineage":["https://openalex.org/I124866261"]}],"countries":["AE"],"is_corresponding":false,"raw_author_name":"Zakaria FadlAlrnoula Himat","raw_affiliation_strings":["College of Engineering and Computing, AIGhurair University, Dubai, UAE"],"affiliations":[{"raw_affiliation_string":"College of Engineering and Computing, AIGhurair University, Dubai, UAE","institution_ids":["https://openalex.org/I124866261"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5015702025"],"corresponding_institution_ids":["https://openalex.org/I161913731"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.13654617,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"4","issue":null,"first_page":"1037","last_page":"1040"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.9550257921218872},{"id":"https://openalex.org/keywords/power\u2013delay-product","display_name":"Power\u2013delay product","score":0.7965432405471802},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6545212864875793},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5873903036117554},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5480296611785889},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5026063919067383},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.48692643642425537},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.47127100825309753},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4594283103942871},{"id":"https://openalex.org/keywords/low-power-electronics","display_name":"Low-power electronics","score":0.41485509276390076},{"id":"https://openalex.org/keywords/carry-save-adder","display_name":"Carry-save adder","score":0.41211581230163574},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22376790642738342},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.06318804621696472}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.9550257921218872},{"id":"https://openalex.org/C2776391166","wikidata":"https://www.wikidata.org/wiki/Q7236873","display_name":"Power\u2013delay product","level":4,"score":0.7965432405471802},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6545212864875793},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5873903036117554},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5480296611785889},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5026063919067383},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.48692643642425537},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.47127100825309753},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4594283103942871},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.41485509276390076},{"id":"https://openalex.org/C3227080","wikidata":"https://www.wikidata.org/wiki/Q5046770","display_name":"Carry-save adder","level":4,"score":0.41211581230163574},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22376790642738342},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.06318804621696472},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ssd.2018.8570602","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ssd.2018.8570602","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 15th International Multi-Conference on Systems, Signals & Devices (SSD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8999999761581421,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W95478212","https://openalex.org/W1609370892","https://openalex.org/W1662824729","https://openalex.org/W2069345435","https://openalex.org/W2072842989","https://openalex.org/W2081237810","https://openalex.org/W2083436249","https://openalex.org/W2096767796","https://openalex.org/W2098769011","https://openalex.org/W2135868795","https://openalex.org/W2140950229","https://openalex.org/W2155296713","https://openalex.org/W2260087020","https://openalex.org/W2529692069","https://openalex.org/W2541719535","https://openalex.org/W4253095230","https://openalex.org/W6603827359","https://openalex.org/W6668435955"],"related_works":["https://openalex.org/W2902180427","https://openalex.org/W2339546864","https://openalex.org/W1108467054","https://openalex.org/W4384928667","https://openalex.org/W2914874591","https://openalex.org/W2181740462","https://openalex.org/W2779967057","https://openalex.org/W2186469553","https://openalex.org/W1984380294","https://openalex.org/W2333351870"],"abstract_inverted_index":{"This":[0,53],"paper":[1],"presents":[2],"the":[3,45,50,58,63,68,76,81,85,101,115],"design":[4,40,65],"and":[5,26,36,100],"characterization":[6],"of":[7],"a":[8,16],"threshold":[9],"logic":[10],"adder.":[11],"The":[12,22,93,109],"proposed":[13],"adder":[14,23,82],"has":[15,55,79,88],"regular":[17],"structure":[18],"comprising":[19],"11":[20],"inverters.":[21],"was":[24,42,103,112],"designed":[25],"simulated":[27],"in":[28,90],"three":[29],"nano-scale":[30],"technologies:":[31],"32":[32],"nm,":[33,35],"22":[34],"16":[37,116],"nm.":[38],"A":[39],"technique":[41,54,78],"applied":[43],"at":[44,114],"device":[46],"level":[47],"to":[48,62,98,107],"reduce":[49],"power":[51,74,94],"consumption.":[52],"significantly":[56],"reduced":[57,104],"power,":[59],"as":[60],"compared":[61],"classical":[64],"method.":[66],"Since":[67],"speed":[69],"is":[70],"typically":[71],"traded-off":[72],"for":[73],"consumption,":[75],"new":[77],"increased":[80],"delay.":[83],"However,":[84],"power-delay-product":[86],"(PDP)":[87],"decreased":[89,95],"all":[91],"technologies.":[92],"by":[96,105],"up":[97,106],"88%,":[99],"PDP":[102],"55%.":[108],"largest":[110],"improvement":[111],"observed":[113],"nm":[117],"technology":[118],"node.":[119]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}