{"id":"https://openalex.org/W1949070338","doi":"https://doi.org/10.1109/softcom.2015.7314103","title":"Low power methodology for an ASIC design flow based on high-level synthesis","display_name":"Low power methodology for an ASIC design flow based on high-level synthesis","publication_year":2015,"publication_date":"2015-09-01","ids":{"openalex":"https://openalex.org/W1949070338","doi":"https://doi.org/10.1109/softcom.2015.7314103","mag":"1949070338"},"language":"en","primary_location":{"id":"doi:10.1109/softcom.2015.7314103","is_oa":false,"landing_page_url":"https://doi.org/10.1109/softcom.2015.7314103","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 23rd International Conference on Software, Telecommunications and Computer Networks (SoftCOM)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037596497","display_name":"Fahad Bin Muslim","orcid":"https://orcid.org/0000-0002-4153-360X"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Fahad Bin Muslim","raw_affiliation_strings":["Department of Electronics and Telecommunication Politecnico di Torino, ITALY","Dept of Electronics and Telecommunication, Politecnico di Torino, Italy#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Telecommunication Politecnico di Torino, ITALY","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Dept of Electronics and Telecommunication, Politecnico di Torino, Italy#TAB#","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046608206","display_name":"Affaq Qamar","orcid":"https://orcid.org/0000-0002-4350-4677"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Affaq Qamar","raw_affiliation_strings":["Department of Electronics and Telecommunication Politecnico di Torino, ITALY","Dept of Electronics and Telecommunication, Politecnico di Torino, Italy#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Telecommunication Politecnico di Torino, ITALY","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Dept of Electronics and Telecommunication, Politecnico di Torino, Italy#TAB#","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5050365912","display_name":"Luciano Lavagno","orcid":"https://orcid.org/0000-0002-9762-6522"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Luciano Lavagno","raw_affiliation_strings":["Department of Electronics and Telecommunication Politecnico di Torino, ITALY","Dept of Electronics and Telecommunication, Politecnico di Torino, Italy#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Telecommunication Politecnico di Torino, ITALY","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Dept of Electronics and Telecommunication, Politecnico di Torino, Italy#TAB#","institution_ids":["https://openalex.org/I177477856"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5037596497"],"corresponding_institution_ids":["https://openalex.org/I177477856"],"apc_list":null,"apc_paid":null,"fwci":0.5918,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.71691025,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"11","last_page":"15"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.8777166604995728},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.761645495891571},{"id":"https://openalex.org/keywords/dynamic-demand","display_name":"Dynamic demand","score":0.6790937185287476},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6444333791732788},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.5493060946464539},{"id":"https://openalex.org/keywords/power-domains","display_name":"Power domains","score":0.5489455461502075},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5367570519447327},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5108930468559265},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5074264407157898},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.484592080116272},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.47018635272979736},{"id":"https://openalex.org/keywords/power-optimization","display_name":"Power optimization","score":0.45356911420822144},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.44464579224586487},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.4337516725063324},{"id":"https://openalex.org/keywords/low-power-electronics","display_name":"Low-power electronics","score":0.4189385771751404},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2689089775085449},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.23016729950904846},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.1907522976398468},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.15905430912971497},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.14615371823310852},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.14330217242240906},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.13884344696998596}],"concepts":[{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.8777166604995728},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.761645495891571},{"id":"https://openalex.org/C45872418","wikidata":"https://www.wikidata.org/wiki/Q5318966","display_name":"Dynamic demand","level":3,"score":0.6790937185287476},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6444333791732788},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5493060946464539},{"id":"https://openalex.org/C16021271","wikidata":"https://www.wikidata.org/wiki/Q17152552","display_name":"Power domains","level":3,"score":0.5489455461502075},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5367570519447327},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5108930468559265},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5074264407157898},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.484592080116272},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.47018635272979736},{"id":"https://openalex.org/C168292644","wikidata":"https://www.wikidata.org/wiki/Q10860336","display_name":"Power optimization","level":4,"score":0.45356911420822144},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.44464579224586487},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.4337516725063324},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.4189385771751404},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2689089775085449},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.23016729950904846},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.1907522976398468},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.15905430912971497},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.14615371823310852},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.14330217242240906},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.13884344696998596},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/softcom.2015.7314103","is_oa":false,"landing_page_url":"https://doi.org/10.1109/softcom.2015.7314103","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 23rd International Conference on Software, Telecommunications and Computer Networks (SoftCOM)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8799999952316284,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W86524118","https://openalex.org/W119030859","https://openalex.org/W2021726431","https://openalex.org/W2034674049","https://openalex.org/W2035369415","https://openalex.org/W2152979262","https://openalex.org/W2171318521","https://openalex.org/W4237807970","https://openalex.org/W4298335083"],"related_works":["https://openalex.org/W2020434689","https://openalex.org/W2138778793","https://openalex.org/W1949070338","https://openalex.org/W2485892467","https://openalex.org/W2358819000","https://openalex.org/W576646735","https://openalex.org/W2103368706","https://openalex.org/W4252084893","https://openalex.org/W1585590517","https://openalex.org/W2179231821"],"abstract_inverted_index":{"Power":[0,102,160],"management":[1],"in":[2,10,133,152,164],"system-on-chip":[3],"(SoC)":[4],"design":[5,88],"has":[6],"become":[7],"very":[8],"important":[9],"modern":[11],"nanometric":[12],"technologies.":[13],"It":[14],"is":[15,95,104,142,155],"desirable":[16],"to":[17,29,56,66,78],"consider":[18],"power":[19,26,38,48,59,80,109,113,135,154,158],"optimization":[20],"at":[21],"the":[22,63,90,108,120],"system-level":[23],"for":[24,44],"maximum":[25,58],"savings":[27],"due":[28],"its":[30],"higher":[31],"level":[32,93],"of":[33,81,122,139],"abstraction.":[34],"Clock":[35],"gating":[36,39,103,146,161],"and":[37,46],"are":[40],"two":[41],"well-known":[42],"techniques":[43,77],"dynamic":[45,134],"leakage":[47],"reduction":[49,60],"respectively.":[50],"They":[51],"can":[52],"even":[53],"be":[54],"integrated":[55],"get":[57],"by":[61,98,106,136],"using":[62,74,111,129],"same":[64],"signal":[65],"control":[67],"both.":[68],"This":[69,116],"work":[70,117],"presents":[71],"a":[72,137],"methodology":[73],"both":[75],"these":[76],"save":[79],"an":[82],"inverse":[83],"discrete":[84],"cosine":[85],"transform":[86],"(IDCT)":[87],"when":[89],"register":[91],"transfer":[92],"(RTL)":[94],"generated":[96,127],"automatically":[97,126],"high-level":[99],"synthesis":[100],"(HLS).":[101],"implemented":[105],"capturing":[107],"intent":[110],"common":[112],"format":[114],"(CPF).":[115],"mainly":[118],"highlights":[119],"prospects":[121],"integrating":[123],"CPF":[124],"with":[125],"RTL":[128],"HLS":[130],"flow.":[131],"Saving":[132],"factor":[138],"around":[140],"10\u00d7":[141],"obtained":[143,156],"through":[144,157],"clock":[145],"while":[147],"more":[148],"than":[149],"50%":[150],"saving":[151],"static":[153],"gating.":[159],"also":[162],"results":[163],"some":[165],"area":[166],"overhead.":[167]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1}],"updated_date":"2025-12-13T23:11:00.310470","created_date":"2025-10-10T00:00:00"}