{"id":"https://openalex.org/W2070648266","doi":"https://doi.org/10.1109/soccon.2009.5398024","title":"DDR3 based lookup circuit for high-performance network processing","display_name":"DDR3 based lookup circuit for high-performance network processing","publication_year":2009,"publication_date":"2009-09-01","ids":{"openalex":"https://openalex.org/W2070648266","doi":"https://doi.org/10.1109/soccon.2009.5398024","mag":"2070648266"},"language":"en","primary_location":{"id":"doi:10.1109/soccon.2009.5398024","is_oa":false,"landing_page_url":"https://doi.org/10.1109/soccon.2009.5398024","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International SOC Conference (SOCC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://pureadmin.qub.ac.uk/ws/files/18189259/PID932288_SOCC_Xin.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5115587895","display_name":"Xin Yang","orcid":"https://orcid.org/0009-0009-8634-3760"},"institutions":[{"id":"https://openalex.org/I126231945","display_name":"Queen's University Belfast","ror":"https://ror.org/00hswnk62","country_code":"GB","type":"education","lineage":["https://openalex.org/I126231945"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Xin Yang","raw_affiliation_strings":["ECIT Institute, Queen's University Belfast, UK","ECIT Institute, Queen\u00bfs University Belfast, Northern Ireland, UK"],"affiliations":[{"raw_affiliation_string":"ECIT Institute, Queen's University Belfast, UK","institution_ids":["https://openalex.org/I126231945"]},{"raw_affiliation_string":"ECIT Institute, Queen\u00bfs University Belfast, Northern Ireland, UK","institution_ids":["https://openalex.org/I126231945"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103745938","display_name":"Sakir Sezer","orcid":null},"institutions":[{"id":"https://openalex.org/I126231945","display_name":"Queen's University Belfast","ror":"https://ror.org/00hswnk62","country_code":"GB","type":"education","lineage":["https://openalex.org/I126231945"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Sakir Sezer","raw_affiliation_strings":["ECIT Institute, Queen's University Belfast, UK","ECIT Institute, Queen\u00bfs University Belfast, Northern Ireland, UK"],"affiliations":[{"raw_affiliation_string":"ECIT Institute, Queen's University Belfast, UK","institution_ids":["https://openalex.org/I126231945"]},{"raw_affiliation_string":"ECIT Institute, Queen\u00bfs University Belfast, Northern Ireland, UK","institution_ids":["https://openalex.org/I126231945"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111565223","display_name":"J.V. McCanny","orcid":null},"institutions":[{"id":"https://openalex.org/I126231945","display_name":"Queen's University Belfast","ror":"https://ror.org/00hswnk62","country_code":"GB","type":"education","lineage":["https://openalex.org/I126231945"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"John McCanny","raw_affiliation_strings":["ECIT Institute, Queen's University Belfast, UK","ECIT Institute, Queen\u00bfs University Belfast, Northern Ireland, UK"],"affiliations":[{"raw_affiliation_string":"ECIT Institute, Queen's University Belfast, UK","institution_ids":["https://openalex.org/I126231945"]},{"raw_affiliation_string":"ECIT Institute, Queen\u00bfs University Belfast, Northern Ireland, UK","institution_ids":["https://openalex.org/I126231945"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5049177697","display_name":"Dwayne Burns","orcid":null},"institutions":[{"id":"https://openalex.org/I126231945","display_name":"Queen's University Belfast","ror":"https://ror.org/00hswnk62","country_code":"GB","type":"education","lineage":["https://openalex.org/I126231945"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Dwayne Burns","raw_affiliation_strings":["ECIT Institute, Queen's University Belfast, UK","ECIT Institute, Queen\u00bfs University Belfast, Northern Ireland, UK"],"affiliations":[{"raw_affiliation_string":"ECIT Institute, Queen's University Belfast, UK","institution_ids":["https://openalex.org/I126231945"]},{"raw_affiliation_string":"ECIT Institute, Queen\u00bfs University Belfast, Northern Ireland, UK","institution_ids":["https://openalex.org/I126231945"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5115587895"],"corresponding_institution_ids":["https://openalex.org/I126231945"],"apc_list":null,"apc_paid":null,"fwci":0.5355,"has_fulltext":true,"cited_by_count":4,"citation_normalized_percentile":{"value":0.67041907,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"351","last_page":"354"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7690939903259277},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.6971578598022461},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.6633135676383972},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.5435059666633606},{"id":"https://openalex.org/keywords/physical-address","display_name":"Physical address","score":0.4417233467102051},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.43277284502983093},{"id":"https://openalex.org/keywords/memory-map","display_name":"Memory map","score":0.42471978068351746},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.41926687955856323},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.4136075973510742},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3867930769920349},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.17576450109481812}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7690939903259277},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.6971578598022461},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.6633135676383972},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.5435059666633606},{"id":"https://openalex.org/C41036726","wikidata":"https://www.wikidata.org/wiki/Q844824","display_name":"Physical address","level":3,"score":0.4417233467102051},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.43277284502983093},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.42471978068351746},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.41926687955856323},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.4136075973510742},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3867930769920349},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.17576450109481812}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/soccon.2009.5398024","is_oa":false,"landing_page_url":"https://doi.org/10.1109/soccon.2009.5398024","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International SOC Conference (SOCC)","raw_type":"proceedings-article"},{"id":"pmh:oai:pure.qub.ac.uk/portal:openaire/00f4afa8-13f7-461a-87f2-523c5c871714","is_oa":true,"landing_page_url":"https://pure.qub.ac.uk/en/publications/00f4afa8-13f7-461a-87f2-523c5c871714","pdf_url":"https://pureadmin.qub.ac.uk/ws/files/18189259/PID932288_SOCC_Xin.pdf","source":{"id":"https://openalex.org/S4306402319","display_name":"Research Portal (Queen's University Belfast)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I126231945","host_organization_name":"Queen's University Belfast","host_organization_lineage":["https://openalex.org/I126231945"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Yang, X, Sezer, S, McCanny, J & Burns, D 2009, 'DDR3 Based Lookup Circuit For High-Performance Network Processing', Paper presented at IEEE International SOC Conference (SOCC), Belfast, United Kingdom, 01/09/2009 - 01/09/2009 pp. 351-354. https://doi.org/10.1109/SOCCON.2009.5398024","raw_type":"info:eu-repo/semantics/conferenceObject"},{"id":"pmh:oai:pure.qub.ac.uk/portal:publications/00f4afa8-13f7-461a-87f2-523c5c871714","is_oa":true,"landing_page_url":"http://www.scopus.com/inward/record.url?scp=77949601314&partnerID=8YFLogxK","pdf_url":null,"source":{"id":"https://openalex.org/S4306402319","display_name":"Research Portal (Queen's University Belfast)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I126231945","host_organization_name":"Queen's University Belfast","host_organization_lineage":["https://openalex.org/I126231945"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Yang , X , Sezer , S , McCanny , J &amp; Burns , D 2009 , ' DDR3 Based Lookup Circuit For High-Performance Network Processing ' , Paper presented at IEEE International SOC Conference (SOCC) , Belfast , United Kingdom , 01/09/2009 - 01/09/2009 pp. 351-354 . https://doi.org/10.1109/SOCCON.2009.5398024","raw_type":"conferenceObject"}],"best_oa_location":{"id":"pmh:oai:pure.qub.ac.uk/portal:openaire/00f4afa8-13f7-461a-87f2-523c5c871714","is_oa":true,"landing_page_url":"https://pure.qub.ac.uk/en/publications/00f4afa8-13f7-461a-87f2-523c5c871714","pdf_url":"https://pureadmin.qub.ac.uk/ws/files/18189259/PID932288_SOCC_Xin.pdf","source":{"id":"https://openalex.org/S4306402319","display_name":"Research Portal (Queen's University Belfast)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I126231945","host_organization_name":"Queen's University Belfast","host_organization_lineage":["https://openalex.org/I126231945"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Yang, X, Sezer, S, McCanny, J & Burns, D 2009, 'DDR3 Based Lookup Circuit For High-Performance Network Processing', Paper presented at IEEE International SOC Conference (SOCC), Belfast, United Kingdom, 01/09/2009 - 01/09/2009 pp. 351-354. https://doi.org/10.1109/SOCCON.2009.5398024","raw_type":"info:eu-repo/semantics/conferenceObject"},"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320320357","display_name":"Queen's University Belfast","ror":"https://ror.org/00hswnk62"},{"id":"https://openalex.org/F4320321832","display_name":"Queen's University","ror":"https://ror.org/02y72wh86"}],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2070648266.pdf","grobid_xml":"https://content.openalex.org/works/W2070648266.grobid-xml"},"referenced_works_count":10,"referenced_works":["https://openalex.org/W1978464037","https://openalex.org/W2106727979","https://openalex.org/W2111200383","https://openalex.org/W2136004815","https://openalex.org/W2137231558","https://openalex.org/W2188487546","https://openalex.org/W2537482094","https://openalex.org/W3005083674","https://openalex.org/W6640548311","https://openalex.org/W6676019231"],"related_works":["https://openalex.org/W2491097902","https://openalex.org/W2155373950","https://openalex.org/W773491645","https://openalex.org/W1554378476","https://openalex.org/W4243618206","https://openalex.org/W2552325249","https://openalex.org/W2057195881","https://openalex.org/W2044064773","https://openalex.org/W2138825797","https://openalex.org/W2376756065"],"abstract_inverted_index":{"Double":[0],"Data":[1],"Rate":[2],"(DDR)":[3],"SDRAMs":[4],"have":[5],"been":[6],"prevalent":[7],"in":[8,13],"the":[9,42,61,87],"PC":[10],"memory":[11,24,33,49,55,62],"market":[12],"recent":[14],"years":[15],"and":[16,35,46,80],"are":[17,26],"widely":[18],"used":[19],"for":[20,59,74],"networking":[21],"systems.":[22],"These":[23],"devices":[25],"rapidly":[27],"developing,":[28],"with":[29],"high":[30,32],"density,":[31],"bandwidth":[34],"low":[36],"device":[37],"cost.":[38],"However,":[39],"because":[40],"of":[41],"high-speed":[43],"interface":[44],"technology":[45],"complex":[47],"instruction-based":[48],"access":[50,63],"control,":[51],"a":[52,69,81],"specific":[53,70],"purpose":[54,71],"controller":[56,73],"is":[57,78,90],"necessary":[58],"optimizing":[60],"trade":[64],"off.":[65],"In":[66],"this":[67],"paper,":[68],"DDR3":[72],"high-performance":[75],"table":[76],"lookup":[77,83],"proposed":[79],"corresponding":[82],"circuit":[84],"based":[85],"on":[86],"Hash-CAM":[88],"approach":[89],"presented.":[91]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
