{"id":"https://openalex.org/W4416342186","doi":"https://doi.org/10.1109/socc66126.2025.11235475","title":"A DNN-Oriented Rapid Simulation Framework for Digital Processing-In-Memory Architectures","display_name":"A DNN-Oriented Rapid Simulation Framework for Digital Processing-In-Memory Architectures","publication_year":2025,"publication_date":"2025-09-29","ids":{"openalex":"https://openalex.org/W4416342186","doi":"https://doi.org/10.1109/socc66126.2025.11235475"},"language":null,"primary_location":{"id":"doi:10.1109/socc66126.2025.11235475","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc66126.2025.11235475","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE 38th International System-on-Chip Conference (SOCC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051037426","display_name":"Yirong Kan","orcid":"https://orcid.org/0000-0002-4070-0672"},"institutions":[{"id":"https://openalex.org/I75917431","display_name":"Nara Institute of Science and Technology","ror":"https://ror.org/05bhada84","country_code":"JP","type":"education","lineage":["https://openalex.org/I75917431"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yirong Kan","raw_affiliation_strings":["Nara Institute of Science and Technology,Division of Information Science,Ikoma,Japan,630-0192"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Nara Institute of Science and Technology,Division of Information Science,Ikoma,Japan,630-0192","institution_ids":["https://openalex.org/I75917431"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054574728","display_name":"Guangxian Zhu","orcid":"https://orcid.org/0009-0004-3340-4789"},"institutions":[{"id":"https://openalex.org/I75917431","display_name":"Nara Institute of Science and Technology","ror":"https://ror.org/05bhada84","country_code":"JP","type":"education","lineage":["https://openalex.org/I75917431"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Guangxian Zhu","raw_affiliation_strings":["Nara Institute of Science and Technology,Division of Information Science,Ikoma,Japan,630-0192"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Nara Institute of Science and Technology,Division of Information Science,Ikoma,Japan,630-0192","institution_ids":["https://openalex.org/I75917431"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101464173","display_name":"Renyuan Zhang","orcid":"https://orcid.org/0000-0002-2635-2077"},"institutions":[{"id":"https://openalex.org/I189210763","display_name":"Yunnan University","ror":"https://ror.org/0040axw97","country_code":"CN","type":"education","lineage":["https://openalex.org/I189210763"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Renyuan Zhang","raw_affiliation_strings":["Yunnan University,School of Information Science and Engineering,Kunming,China,650091"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Yunnan University,School of Information Science and Engineering,Kunming,China,650091","institution_ids":["https://openalex.org/I189210763"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074853381","display_name":"Yasuhiko Nakashima","orcid":"https://orcid.org/0000-0002-9457-5061"},"institutions":[{"id":"https://openalex.org/I75917431","display_name":"Nara Institute of Science and Technology","ror":"https://ror.org/05bhada84","country_code":"JP","type":"education","lineage":["https://openalex.org/I75917431"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yasuhiko Nakashima","raw_affiliation_strings":["Nara Institute of Science and Technology,Division of Information Science,Ikoma,Japan,630-0192"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Nara Institute of Science and Technology,Division of Information Science,Ikoma,Japan,630-0192","institution_ids":["https://openalex.org/I75917431"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.29590665,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.6865000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.6865000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.181099995970726,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10036","display_name":"Advanced Neural Network Applications","score":0.057100001722574234,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.642300009727478},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.573199987411499},{"id":"https://openalex.org/keywords/parameterized-complexity","display_name":"Parameterized complexity","score":0.4896000027656555},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.40700000524520874},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.3589000105857849},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.3467999994754791},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.3131999969482422},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.3100000023841858}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7146999835968018},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.642300009727478},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6399000287055969},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.573199987411499},{"id":"https://openalex.org/C165464430","wikidata":"https://www.wikidata.org/wiki/Q1570441","display_name":"Parameterized complexity","level":2,"score":0.4896000027656555},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.40700000524520874},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3970000147819519},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3772999942302704},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.3589000105857849},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.3467999994754791},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.3131999969482422},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.3100000023841858},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.2937999963760376},{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.2903999984264374},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.288100004196167},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.2773999869823456},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.272599995136261},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.2678999900817871},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.26190000772476196},{"id":"https://openalex.org/C108583219","wikidata":"https://www.wikidata.org/wiki/Q197536","display_name":"Deep learning","level":2,"score":0.2549999952316284},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.2538999915122986},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.2524999976158142}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/socc66126.2025.11235475","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc66126.2025.11235475","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE 38th International System-on-Chip Conference (SOCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1995562189","https://openalex.org/W2041420601","https://openalex.org/W2112796928","https://openalex.org/W2194775991","https://openalex.org/W2289252105","https://openalex.org/W2618530766","https://openalex.org/W2782046614","https://openalex.org/W2944987128","https://openalex.org/W2945707356","https://openalex.org/W2963446712","https://openalex.org/W2974067241","https://openalex.org/W3005619596","https://openalex.org/W3033519076","https://openalex.org/W3036436862","https://openalex.org/W3135906938","https://openalex.org/W3214267057","https://openalex.org/W4225943547","https://openalex.org/W4280502333","https://openalex.org/W4381050415","https://openalex.org/W4385245566","https://openalex.org/W4390119970"],"related_works":[],"abstract_inverted_index":{"Processing-In-Memory":[0],"(PIM)":[1],"architectures":[2,14,66],"show":[3],"great":[4],"potential":[5],"in":[6,32],"accelerating":[7],"deep":[8],"neural":[9],"networks":[10],"(DNNs).":[11],"Although":[12],"PIM":[13,56,65,98,137,161],"based":[15],"on":[16,135,148],"various":[17,78],"memory":[18],"devices":[19],"have":[20],"been":[21],"developed,":[22],"it":[23],"is":[24,119],"challenging":[25],"to":[26,92,126,153,157],"rapidly":[27],"estimate":[28],"performance":[29,108,143],"of":[30,54,64,96,105,132,144],"chips":[31],"the":[33,88,94,97,110,117,141,145],"early":[34],"design":[35,50],"stage.":[36],"In":[37,115],"this":[38],"paper,":[39],"we":[40],"propose":[41],"a":[42],"modular":[43],"and":[44,51,74,82,130],"parameterized":[45],"simulation":[46,63],"framework":[47,60,89,118,125,147],"DDSim,":[48],"for":[49],"rapid":[52,86],"estimation":[53],"digital":[55,136,160],"architectures.":[57,138,162],"The":[58],"proposed":[59,146],"supports":[61],"fast":[62,158],"at":[67,109],"three":[68],"levels:":[69],"chip":[70],"level,":[71,73,76],"tile":[72],"array":[75],"providing":[77],"trade-offs":[79],"between":[80],"speed":[81],"accuracy.":[83],"To":[84],"enable":[85,127],"simulation,":[87],"allow":[90],"users":[91],"customize":[93],"parameters":[95],"architecture":[99],"with":[100,122],"pre-synthesis":[101],"logic":[102],"units,":[103],"instead":[104],"estimating":[106],"hardware":[107],"transistor":[111],"level":[112],"every":[113],"time.":[114],"addtion,":[116],"tightly":[120],"coupled":[121],"Pytorch-based":[123],"DNN":[124,133,151],"automatic":[128],"extraction":[129],"mapping":[131],"models":[134,152],"We":[139],"demonstrate":[140],"benchmark":[142],"several":[149],"typical":[150],"prove":[154],"its":[155],"ability":[156],"simulate":[159]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-11-17T00:00:00"}
