{"id":"https://openalex.org/W4416342034","doi":"https://doi.org/10.1109/socc66126.2025.11235402","title":"Performance Impact of Caches, Interrupt Strategies and Communication on SoC Lookaside Acceleration","display_name":"Performance Impact of Caches, Interrupt Strategies and Communication on SoC Lookaside Acceleration","publication_year":2025,"publication_date":"2025-09-29","ids":{"openalex":"https://openalex.org/W4416342034","doi":"https://doi.org/10.1109/socc66126.2025.11235402"},"language":"en","primary_location":{"id":"doi:10.1109/socc66126.2025.11235402","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc66126.2025.11235402","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE 38th International System-on-Chip Conference (SOCC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://pure.qub.ac.uk/en/publications/b2e5b33d-ecd3-4077-b06a-33f2df65f880","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5005067066","display_name":"Alperen Bolat","orcid":"https://orcid.org/0000-0003-0170-8038"},"institutions":[{"id":"https://openalex.org/I126231945","display_name":"Queen's University Belfast","ror":"https://ror.org/00hswnk62","country_code":"GB","type":"education","lineage":["https://openalex.org/I126231945"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Alperen Bolat","raw_affiliation_strings":["Queen’s University Belfast,Belfast,UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Queen’s University Belfast,Belfast,UK","institution_ids":["https://openalex.org/I126231945"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103745938","display_name":"Sakir Sezer","orcid":null},"institutions":[{"id":"https://openalex.org/I126231945","display_name":"Queen's University Belfast","ror":"https://ror.org/00hswnk62","country_code":"GB","type":"education","lineage":["https://openalex.org/I126231945"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Sakir Sezer","raw_affiliation_strings":["Queen’s University Belfast,Belfast,UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Queen’s University Belfast,Belfast,UK","institution_ids":["https://openalex.org/I126231945"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027789250","display_name":"Kieran McLaughlin","orcid":"https://orcid.org/0000-0002-1299-2364"},"institutions":[{"id":"https://openalex.org/I126231945","display_name":"Queen's University Belfast","ror":"https://ror.org/00hswnk62","country_code":"GB","type":"education","lineage":["https://openalex.org/I126231945"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Kieran Mclaughlin","raw_affiliation_strings":["Queen’s University Belfast,Belfast,UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Queen’s University Belfast,Belfast,UK","institution_ids":["https://openalex.org/I126231945"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019007983","display_name":"Henry Hui","orcid":"https://orcid.org/0000-0002-8981-5462"},"institutions":[{"id":"https://openalex.org/I126231945","display_name":"Queen's University Belfast","ror":"https://ror.org/00hswnk62","country_code":"GB","type":"education","lineage":["https://openalex.org/I126231945"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Henry Hui","raw_affiliation_strings":["Queen’s University Belfast,Belfast,UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Queen’s University Belfast,Belfast,UK","institution_ids":["https://openalex.org/I126231945"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5085690468","display_name":"Fatih Kurug\u00f6ll\u00fc","orcid":"https://orcid.org/0000-0002-2508-4496"},"institutions":[{"id":"https://openalex.org/I29891158","display_name":"University of Sharjah","ror":"https://ror.org/00engpz63","country_code":"AE","type":"education","lineage":["https://openalex.org/I29891158"]}],"countries":["AE"],"is_corresponding":false,"raw_author_name":"Fatih Kurugollu","raw_affiliation_strings":["University of Sharjah,Sharjah,UAE"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Sharjah,Sharjah,UAE","institution_ids":["https://openalex.org/I29891158"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":true,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.929099977016449,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.929099977016449,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.019200000911951065,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.013299999758601189,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interrupt","display_name":"Interrupt","score":0.7961999773979187},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.609000027179718},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.4984999895095825},{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.4814999997615814},{"id":"https://openalex.org/keywords/acceleration","display_name":"Acceleration","score":0.46619999408721924},{"id":"https://openalex.org/keywords/workload","display_name":"Workload","score":0.45249998569488525},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.4221000075340271},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.4196999967098236}],"concepts":[{"id":"https://openalex.org/C41661131","wikidata":"https://www.wikidata.org/wiki/Q220764","display_name":"Interrupt","level":3,"score":0.7961999773979187},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.7249000072479248},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6793000102043152},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.609000027179718},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.4984999895095825},{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.4814999997615814},{"id":"https://openalex.org/C117896860","wikidata":"https://www.wikidata.org/wiki/Q11376","display_name":"Acceleration","level":2,"score":0.46619999408721924},{"id":"https://openalex.org/C2778476105","wikidata":"https://www.wikidata.org/wiki/Q628539","display_name":"Workload","level":2,"score":0.45249998569488525},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4221000075340271},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.4196999967098236},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.375},{"id":"https://openalex.org/C77495112","wikidata":"https://www.wikidata.org/wiki/Q5358436","display_name":"Electronic system-level design and verification","level":2,"score":0.36390000581741333},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.3598000109195709},{"id":"https://openalex.org/C26771161","wikidata":"https://www.wikidata.org/wiki/Q16980","display_name":"ARM architecture","level":2,"score":0.34040001034736633},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.33559998869895935},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.3296999931335449},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.326200008392334},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.32089999318122864},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.3100999891757965},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.3003000020980835},{"id":"https://openalex.org/C31352089","wikidata":"https://www.wikidata.org/wiki/Q3750474","display_name":"Systems design","level":2,"score":0.26899999380111694},{"id":"https://openalex.org/C2778915421","wikidata":"https://www.wikidata.org/wiki/Q3643177","display_name":"Performance improvement","level":2,"score":0.2662999927997589},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.25529998540878296}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/socc66126.2025.11235402","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc66126.2025.11235402","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE 38th International System-on-Chip Conference (SOCC)","raw_type":"proceedings-article"},{"id":"pmh:oai:pure.qub.ac.uk/portal:openaire/b2e5b33d-ecd3-4077-b06a-33f2df65f880","is_oa":true,"landing_page_url":"https://pure.qub.ac.uk/en/publications/b2e5b33d-ecd3-4077-b06a-33f2df65f880","pdf_url":null,"source":{"id":"https://openalex.org/S4306402319","display_name":"Research Portal (Queen's University Belfast)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I126231945","host_organization_name":"Queen's University Belfast","host_organization_lineage":["https://openalex.org/I126231945"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Bolat, A, Sezer, S, McLaughlin, K, Hui, H & Kurugollu, F 2025, Performance impact of caches, interrupt strategies and communication on SoC lookaside acceleration. in 2025 38th IEEE International System-on-Chip Conference (SOCC): proceedings. IEEE International System-on-Chip Conference (SOCC): proceedings, IEEE, 38th IEEE International System-on-Chip Conference (SOCC 2025), 29/09/2025. https://doi.org/10.1109/SOCC66126.2025.11235402","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":{"id":"pmh:oai:pure.qub.ac.uk/portal:openaire/b2e5b33d-ecd3-4077-b06a-33f2df65f880","is_oa":true,"landing_page_url":"https://pure.qub.ac.uk/en/publications/b2e5b33d-ecd3-4077-b06a-33f2df65f880","pdf_url":null,"source":{"id":"https://openalex.org/S4306402319","display_name":"Research Portal (Queen's University Belfast)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I126231945","host_organization_name":"Queen's University Belfast","host_organization_lineage":["https://openalex.org/I126231945"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Bolat, A, Sezer, S, McLaughlin, K, Hui, H & Kurugollu, F 2025, Performance impact of caches, interrupt strategies and communication on SoC lookaside acceleration. in 2025 38th IEEE International System-on-Chip Conference (SOCC): proceedings. IEEE International System-on-Chip Conference (SOCC): proceedings, IEEE, 38th IEEE International System-on-Chip Conference (SOCC 2025), 29/09/2025. https://doi.org/10.1109/SOCC66126.2025.11235402","raw_type":"info:eu-repo/semantics/conferenceObject"},"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320314204","display_name":"Invest Northern Ireland","ror":"https://ror.org/00qnrsq87"},{"id":"https://openalex.org/F4320314707","display_name":"Government of the United Kingdom","ror":"https://ror.org/05wnh3t63"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W2054193768","https://openalex.org/W2064156449","https://openalex.org/W2906989145","https://openalex.org/W2910602046","https://openalex.org/W2980002395","https://openalex.org/W3177763227","https://openalex.org/W4323527478","https://openalex.org/W4386953138","https://openalex.org/W4388298400"],"related_works":[],"abstract_inverted_index":{"Lookaside":[0],"Accelerators":[1],"(LAAs)":[2],"present":[3],"a":[4],"compelling":[5],"approach":[6],"to":[7,56,129,181],"enhancing":[8],"system":[9,34],"performance":[10,47,117,162,184],"by":[11],"offloading":[12],"computational":[13],"workloads":[14],"from":[15,124],"general-purpose":[16],"CPUs,":[17],"offering":[18],"substantial":[19],"potential":[20],"for":[21,176],"next-generation":[22],"accelerated":[23],"computing.":[24],"However,":[25],"the":[26,52,116,130,135,144,152,160],"effectiveness":[27],"of":[28,119,138,141,146,163],"LAAs":[29],"is":[30],"heavily":[31],"dependent":[32],"on":[33,66,99,159],"architecture,":[35],"particularly":[36],"in":[37,59,185],"mitigating":[38],"communication":[39,57,80,161,169],"overhead":[40,58,170],"and":[41,79,151,172,187],"inefficiencies":[42],"that":[43],"can":[44],"hinder":[45],"anticipated":[46],"gains.":[48],"This":[49],"study":[50],"investigates":[51],"key":[53],"factors":[54],"contributing":[55],"LAA-enabled":[60],"architectures,":[61],"analyzing":[62],"their":[63],"collective":[64],"impact":[65,137],"performance.":[67],"Specifically,":[68],"we":[69,91,114],"evaluate":[70],"critical":[71],"architectural":[72],"considerations,":[73],"including":[74],"cache":[75],"hierarchy,":[76],"data-sharing":[77],"mechanisms,":[78],"strategies":[81],"such":[82],"as":[83],"interrupt-driven":[84],"versus":[85],"polling-based":[86],"interactions.To":[87],"assess":[88],"these":[89],"factors,":[90],"implement":[92],"an":[93,96,100,107,125],"LAA":[94],"using":[95],"emulated":[97],"design":[98,157],"FPGA":[101],"integrated":[102],"with":[103,155,189],"ARM":[104,127],"CPUs":[105],"within":[106],"AMD":[108],"MPSoC":[109],"platform.":[110],"Through":[111],"extensive":[112],"evaluation,":[113],"analyze":[115],"implications":[118],"varying":[120],"data":[121,139],"sizes":[122,140],"offloaded":[123],"embedded":[126,190],"core":[128],"accelerator.":[131],"Our":[132],"findings":[133],"highlight":[134],"significant":[136],"workload":[142],"tasks,":[143],"influence":[145],"shared":[147],"memory":[148],"access":[149],"patterns,":[150],"trade-offs":[153],"associated":[154],"different":[156],"considerations":[158],"accelerators.":[164],"Additionally,":[165],"this":[166],"research":[167],"characterizes":[168],"structures":[171],"provides":[173],"optimization":[174],"insights":[175],"accelerator":[177],"design,":[178],"ultimately":[179],"targeting":[180],"enable":[182],"higher":[183],"SoCs":[186],"MPSoCs":[188],"acceleration":[191],"technologies.":[192]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-11-17T00:00:00"}