{"id":"https://openalex.org/W4416341787","doi":"https://doi.org/10.1109/socc66126.2025.11235391","title":"A 4.266 Gbps/pin LPDDR4X PHY with an Integrated RISC-V Subsystem Optimized for Large Bump Pitch in 12nm FinFET Technology","display_name":"A 4.266 Gbps/pin LPDDR4X PHY with an Integrated RISC-V Subsystem Optimized for Large Bump Pitch in 12nm FinFET Technology","publication_year":2025,"publication_date":"2025-09-29","ids":{"openalex":"https://openalex.org/W4416341787","doi":"https://doi.org/10.1109/socc66126.2025.11235391"},"language":null,"primary_location":{"id":"doi:10.1109/socc66126.2025.11235391","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc66126.2025.11235391","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE 38th International System-on-Chip Conference (SOCC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5074857313","display_name":"Marco Mestice","orcid":"https://orcid.org/0000-0003-2975-3471"},"institutions":[{"id":"https://openalex.org/I73114660","display_name":"University of Applied Sciences Kaiserslautern","ror":"https://ror.org/05dkqa017","country_code":"DE","type":"education","lineage":["https://openalex.org/I73114660"]},{"id":"https://openalex.org/I153267046","display_name":"University of Kaiserslautern","ror":"https://ror.org/04zrf7b53","country_code":"DE","type":"education","lineage":["https://openalex.org/I153267046"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Marco Mestice","raw_affiliation_strings":["University of Kaiserslautern-Landau,Microelectronic Systems Design Research Group,Kaiserslautern,Germany"],"affiliations":[{"raw_affiliation_string":"University of Kaiserslautern-Landau,Microelectronic Systems Design Research Group,Kaiserslautern,Germany","institution_ids":["https://openalex.org/I73114660","https://openalex.org/I153267046"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091775161","display_name":"Johannes Feldmann","orcid":"https://orcid.org/0000-0003-4210-0221"},"institutions":[{"id":"https://openalex.org/I73114660","display_name":"University of Applied Sciences Kaiserslautern","ror":"https://ror.org/05dkqa017","country_code":"DE","type":"education","lineage":["https://openalex.org/I73114660"]},{"id":"https://openalex.org/I153267046","display_name":"University of Kaiserslautern","ror":"https://ror.org/04zrf7b53","country_code":"DE","type":"education","lineage":["https://openalex.org/I153267046"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Johannes Feldmann","raw_affiliation_strings":["University of Kaiserslautern-Landau,Microelectronic Systems Design Research Group,Kaiserslautern,Germany"],"affiliations":[{"raw_affiliation_string":"University of Kaiserslautern-Landau,Microelectronic Systems Design Research Group,Kaiserslautern,Germany","institution_ids":["https://openalex.org/I73114660","https://openalex.org/I153267046"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073743729","display_name":"Jan Lappas","orcid":null},"institutions":[{"id":"https://openalex.org/I73114660","display_name":"University of Applied Sciences Kaiserslautern","ror":"https://ror.org/05dkqa017","country_code":"DE","type":"education","lineage":["https://openalex.org/I73114660"]},{"id":"https://openalex.org/I153267046","display_name":"University of Kaiserslautern","ror":"https://ror.org/04zrf7b53","country_code":"DE","type":"education","lineage":["https://openalex.org/I153267046"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Jan Lappas","raw_affiliation_strings":["University of Kaiserslautern-Landau,Microelectronic Systems Design Research Group,Kaiserslautern,Germany"],"affiliations":[{"raw_affiliation_string":"University of Kaiserslautern-Landau,Microelectronic Systems Design Research Group,Kaiserslautern,Germany","institution_ids":["https://openalex.org/I73114660","https://openalex.org/I153267046"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5107287891","display_name":"Mohammadreza Esmaeilpour","orcid":null},"institutions":[{"id":"https://openalex.org/I73114660","display_name":"University of Applied Sciences Kaiserslautern","ror":"https://ror.org/05dkqa017","country_code":"DE","type":"education","lineage":["https://openalex.org/I73114660"]},{"id":"https://openalex.org/I153267046","display_name":"University of Kaiserslautern","ror":"https://ror.org/04zrf7b53","country_code":"DE","type":"education","lineage":["https://openalex.org/I153267046"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Mohammadreza Esmaeilpour","raw_affiliation_strings":["University of Kaiserslautern-Landau,Microelectronic Systems Design Research Group,Kaiserslautern,Germany"],"affiliations":[{"raw_affiliation_string":"University of Kaiserslautern-Landau,Microelectronic Systems Design Research Group,Kaiserslautern,Germany","institution_ids":["https://openalex.org/I73114660","https://openalex.org/I153267046"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090870819","display_name":"Christian Weis","orcid":"https://orcid.org/0000-0002-4152-0200"},"institutions":[{"id":"https://openalex.org/I153267046","display_name":"University of Kaiserslautern","ror":"https://ror.org/04zrf7b53","country_code":"DE","type":"education","lineage":["https://openalex.org/I153267046"]},{"id":"https://openalex.org/I73114660","display_name":"University of Applied Sciences Kaiserslautern","ror":"https://ror.org/05dkqa017","country_code":"DE","type":"education","lineage":["https://openalex.org/I73114660"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Christian Weis","raw_affiliation_strings":["University of Kaiserslautern-Landau,Microelectronic Systems Design Research Group,Kaiserslautern,Germany"],"affiliations":[{"raw_affiliation_string":"University of Kaiserslautern-Landau,Microelectronic Systems Design Research Group,Kaiserslautern,Germany","institution_ids":["https://openalex.org/I73114660","https://openalex.org/I153267046"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5059285190","display_name":"Norbert Wehn","orcid":"https://orcid.org/0000-0002-9010-086X"},"institutions":[{"id":"https://openalex.org/I153267046","display_name":"University of Kaiserslautern","ror":"https://ror.org/04zrf7b53","country_code":"DE","type":"education","lineage":["https://openalex.org/I153267046"]},{"id":"https://openalex.org/I73114660","display_name":"University of Applied Sciences Kaiserslautern","ror":"https://ror.org/05dkqa017","country_code":"DE","type":"education","lineage":["https://openalex.org/I73114660"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Norbert Wehn","raw_affiliation_strings":["University of Kaiserslautern-Landau,Microelectronic Systems Design Research Group,Kaiserslautern,Germany"],"affiliations":[{"raw_affiliation_string":"University of Kaiserslautern-Landau,Microelectronic Systems Design Research Group,Kaiserslautern,Germany","institution_ids":["https://openalex.org/I73114660","https://openalex.org/I153267046"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5074857313"],"corresponding_institution_ids":["https://openalex.org/I153267046","https://openalex.org/I73114660"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.36933159,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.5544000267982483,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.5544000267982483,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.3840999901294708,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.012199999764561653,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phy","display_name":"PHY","score":0.7537999749183655},{"id":"https://openalex.org/keywords/offset","display_name":"Offset (computer science)","score":0.6434999704360962},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.48500001430511475},{"id":"https://openalex.org/keywords/calibration","display_name":"Calibration","score":0.4429999887943268},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.42910000681877136},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.412200003862381},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.40709999203681946},{"id":"https://openalex.org/keywords/comparator","display_name":"Comparator","score":0.38580000400543213}],"concepts":[{"id":"https://openalex.org/C41918916","wikidata":"https://www.wikidata.org/wiki/Q192727","display_name":"PHY","level":4,"score":0.7537999749183655},{"id":"https://openalex.org/C175291020","wikidata":"https://www.wikidata.org/wiki/Q1156822","display_name":"Offset (computer science)","level":2,"score":0.6434999704360962},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5774000287055969},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5705000162124634},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.48500001430511475},{"id":"https://openalex.org/C165838908","wikidata":"https://www.wikidata.org/wiki/Q736777","display_name":"Calibration","level":2,"score":0.4429999887943268},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.42910000681877136},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4250999987125397},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.412200003862381},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.40709999203681946},{"id":"https://openalex.org/C155745195","wikidata":"https://www.wikidata.org/wiki/Q1164179","display_name":"Comparator","level":3,"score":0.38580000400543213},{"id":"https://openalex.org/C2780023022","wikidata":"https://www.wikidata.org/wiki/Q1338171","display_name":"Compensation (psychology)","level":2,"score":0.38339999318122864},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.3785000145435333},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.3659999966621399},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3400999903678894},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3188999891281128},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.31279999017715454},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.30799999833106995},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3019999861717224},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.2921000123023987},{"id":"https://openalex.org/C19247436","wikidata":"https://www.wikidata.org/wiki/Q192727","display_name":"Physical layer","level":3,"score":0.2847999930381775},{"id":"https://openalex.org/C186967261","wikidata":"https://www.wikidata.org/wiki/Q5082128","display_name":"Mobile device","level":2,"score":0.2800000011920929},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.2743000090122223},{"id":"https://openalex.org/C49319798","wikidata":"https://www.wikidata.org/wiki/Q5502874","display_name":"Frequency offset","level":4,"score":0.2687000036239624},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.26019999384880066},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.25189998745918274}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/socc66126.2025.11235391","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc66126.2025.11235391","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE 38th International System-on-Chip Conference (SOCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W2089395228","https://openalex.org/W2533876529","https://openalex.org/W2594689197","https://openalex.org/W2753209132","https://openalex.org/W2790333238","https://openalex.org/W4237972311","https://openalex.org/W4300973170","https://openalex.org/W4396877787","https://openalex.org/W4402572297","https://openalex.org/W4406892517"],"related_works":[],"abstract_inverted_index":{"Low":[0],"Power":[1],"Double":[2],"Data":[3],"Rate":[4],"4X":[5],"(LPDDR4X)":[6],"is":[7,168],"a":[8,48,93,107,177],"leading":[9],"memory":[10,104],"standard":[11],"for":[12],"mobile":[13],"applications,":[14],"delivering":[15],"data":[16],"rates":[17],"up":[18],"to":[19,40,86],"4266":[20],"Mbps":[21],"with":[22,82],"minimal":[23],"power":[24,186],"consumption.":[25],"However,":[26],"its":[27],"low":[28],"0.6V":[29],"I/O":[30,89],"supply":[31],"voltage":[32],"and":[33,43,72,106,111,135,153,157,185],"tight":[34],"timing":[35],"requirements":[36,187],"pose":[37],"significant":[38],"challenges":[39],"signal":[41],"integrity":[42],"synchronization.":[44],"This":[45],"paper":[46],"presents":[47],"full":[49],"LPDDR4X":[50,178],"physical":[51],"interface":[52,105],"(PHY)":[53],"in":[54,141,155,188],"GlobalFoundries":[55],"12nm":[56],"FinFET":[57],"technology":[58,190],"that":[59,181],"addresses":[60],"these":[61],"issues":[62],"through":[63],"novel":[64],"output":[65,163],"driver":[66],"calibration,":[67],"digitally":[68],"controlled":[69],"delay":[70],"lines,":[71],"de-skewing":[73],"clock":[74,164],"generators.":[75],"We":[76],"further":[77],"incorporate":[78],"On-Die":[79],"Termination":[80],"calibration":[81,110],"comparator":[83],"offset":[84],"compensation":[85],"ensure":[87],"robust":[88],"performance.":[90],"By":[91],"integrating":[92],"RISC-V":[94],"subsystem,":[95],"our":[96],"PHY":[97,179],"enables":[98],"low-level":[99],"software":[100],"control":[101],"of":[102,124,131,151,176],"the":[103,118,122,125,174],"fully":[108],"programmable":[109],"training":[112],"algorithm.":[113],"The":[114,161],"measured":[115,162],"results":[116],"from":[117],"fabricated":[119],"prototype":[120],"confirm":[121],"effectiveness":[123],"proposed":[126],"strategies,":[127],"achieving":[128],"write":[129,149],"margins":[130,150],"300mV/0.61UI":[132],"at":[133,137,145,166],"1.6Gbps":[134],"200mV/0.38UI":[136],"2.133Gbps.":[138],"Post-layout":[139],"simulations":[140],"all":[142],"Process-Voltage-Temperature":[143],"corners":[144,159],"4.266Gbps":[146],"show":[147],"instead":[148],"80mV/0.57UI":[152],"140mV/0.72UI":[154],"worst":[156],"best":[158],"respectively.":[160],"amplitude":[165],"2.133GHz":[167],"160mV":[169],"differential.":[170],"These":[171],"findings":[172],"underscore":[173],"feasibility":[175],"solution":[180],"meets":[182],"stringent":[183],"performance":[184],"advanced":[189],"nodes.":[191]},"counts_by_year":[],"updated_date":"2026-03-07T16:01:11.037858","created_date":"2025-11-17T00:00:00"}
