{"id":"https://openalex.org/W4416342826","doi":"https://doi.org/10.1109/socc66126.2025.11235329","title":"High Performance Flip-Flop Design Using a New Output Latch Scheme in Samsung 2nm GAA Process","display_name":"High Performance Flip-Flop Design Using a New Output Latch Scheme in Samsung 2nm GAA Process","publication_year":2025,"publication_date":"2025-09-29","ids":{"openalex":"https://openalex.org/W4416342826","doi":"https://doi.org/10.1109/socc66126.2025.11235329"},"language":null,"primary_location":{"id":"doi:10.1109/socc66126.2025.11235329","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc66126.2025.11235329","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE 38th International System-on-Chip Conference (SOCC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101190473","display_name":"J.H. Oh","orcid":"https://orcid.org/0000-0003-0205-6748"},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Ji-hwan Oh","raw_affiliation_strings":["Samsung Electronics Inc.,System LSI Division,Hwaseong-si,Republic of Korea,18448"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Samsung Electronics Inc.,System LSI Division,Hwaseong-si,Republic of Korea,18448","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Ah-reum Kim","orcid":null},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Ah-reum Kim","raw_affiliation_strings":["Samsung Electronics Inc.,System LSI Division,Hwaseong-si,Republic of Korea,18448"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Samsung Electronics Inc.,System LSI Division,Hwaseong-si,Republic of Korea,18448","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067269577","display_name":"Won-hyun Choi","orcid":null},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Won-hyun Choi","raw_affiliation_strings":["Samsung Electronics Inc.,System LSI Division,Hwaseong-si,Republic of Korea,18448"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Samsung Electronics Inc.,System LSI Division,Hwaseong-si,Republic of Korea,18448","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5033598033","display_name":"Byung-su Kim","orcid":null},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Byung-su Kim","raw_affiliation_strings":["Samsung Electronics Inc.,System LSI Division,Hwaseong-si,Republic of Korea,18448"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Samsung Electronics Inc.,System LSI Division,Hwaseong-si,Republic of Korea,18448","institution_ids":["https://openalex.org/I2250650973"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.29622263,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9851999878883362,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9851999878883362,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.0031999999191612005,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.0017000000225380063,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.6532999873161316},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.5198000073432922},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5139999985694885},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.5072000026702881},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4943999946117401},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.4690999984741211},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.40700000524520874},{"id":"https://openalex.org/keywords/product","display_name":"Product (mathematics)","score":0.38989999890327454}],"concepts":[{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.6532999873161316},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5418999791145325},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.5198000073432922},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5139999985694885},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.5072000026702881},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4943999946117401},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.47620001435279846},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.4690999984741211},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.40700000524520874},{"id":"https://openalex.org/C90673727","wikidata":"https://www.wikidata.org/wiki/Q901718","display_name":"Product (mathematics)","level":2,"score":0.38989999890327454},{"id":"https://openalex.org/C2776391166","wikidata":"https://www.wikidata.org/wiki/Q7236873","display_name":"Power\u2013delay product","level":4,"score":0.36890000104904175},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3433000147342682},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3398999869823456},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.32190001010894775},{"id":"https://openalex.org/C47446073","wikidata":"https://www.wikidata.org/wiki/Q5165890","display_name":"Control theory (sociology)","level":3,"score":0.31349998712539673},{"id":"https://openalex.org/C155386361","wikidata":"https://www.wikidata.org/wiki/Q1649571","display_name":"Process control","level":3,"score":0.2831999957561493},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.2800000011920929},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.27230000495910645},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2685000002384186},{"id":"https://openalex.org/C192615534","wikidata":"https://www.wikidata.org/wiki/Q7247268","display_name":"Process corners","level":3,"score":0.26339998841285706},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.2632000148296356},{"id":"https://openalex.org/C2778915421","wikidata":"https://www.wikidata.org/wiki/Q3643177","display_name":"Performance improvement","level":2,"score":0.2614000141620636},{"id":"https://openalex.org/C55396564","wikidata":"https://www.wikidata.org/wiki/Q3084971","display_name":"Process design","level":3,"score":0.2596000134944916},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.2587999999523163},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.2529999911785126},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.25130000710487366}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/socc66126.2025.11235329","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc66126.2025.11235329","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE 38th International System-on-Chip Conference (SOCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1995665089","https://openalex.org/W2078992878","https://openalex.org/W2109195618","https://openalex.org/W2113735631","https://openalex.org/W2132046218","https://openalex.org/W2141881829","https://openalex.org/W3163408809"],"related_works":[],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,11,65,75],"novel":[4],"pulse-triggered":[5],"flip-flop":[6,105],"(PTFF)":[7],"architecture":[8],"that":[9,60],"incorporates":[10],"Single":[12],"Stage":[13],"Output":[14],"Latch":[15],"to":[16,32,74],"improve":[17],"CQ":[18,66],"delay":[19,67],"performance.":[20],"Unlike":[21],"conventional":[22,79],"latch":[23],"designs,":[24,80],"the":[25,29,34,61,103],"proposed":[26,62,104],"structure":[27],"simplifies":[28],"output":[30],"stage":[31],"shorten":[33],"critical":[35],"timing":[36],"path":[37],"and":[38,46,87,110],"reduce":[39],"overall":[40],"delay.":[41],"The":[42],"design":[43],"was":[44],"implemented":[45],"evaluated":[47],"using":[48],"Samsung's":[49],"advanced":[50],"2nm":[51],"Gate-All-Around":[52],"(GAA)":[53],"process":[54],"technology.":[55],"Post-layout":[56],"simulation":[57],"results":[58],"demonstrate":[59],"PTFF":[63],"achieves":[64],"reduction":[68],"of":[69],"approximately":[70],"2.5":[71],"ps,":[72],"corresponding":[73],"10%":[76],"improvement":[77,98],"over":[78],"under":[81],"sspg":[82],"corner":[83],"at":[84],"0.685":[85],"V":[86],"125":[88],"C.":[89],"Although":[90],"power":[91],"consumption":[92],"increased":[93],"slightly,":[94],"resulting":[95],"in":[96,99],"no":[97],"Energy-Delay":[100],"Product":[101],"(EDP),":[102],"is":[106],"well-suited":[107],"for":[108],"delay-critical":[109],"high-performance":[111],"applications.":[112]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-11-17T00:00:00"}