{"id":"https://openalex.org/W4386952630","doi":"https://doi.org/10.1109/socc58585.2023.10256860","title":"DCVS Level Shifter for Clock Path","display_name":"DCVS Level Shifter for Clock Path","publication_year":2023,"publication_date":"2023-09-05","ids":{"openalex":"https://openalex.org/W4386952630","doi":"https://doi.org/10.1109/socc58585.2023.10256860"},"language":"en","primary_location":{"id":"doi:10.1109/socc58585.2023.10256860","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc58585.2023.10256860","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE 36th International System-on-Chip Conference (SOCC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100343631","display_name":"Minsu Kim","orcid":"https://orcid.org/0000-0002-7179-6929"},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"Min-Su Kim","raw_affiliation_strings":["Samsung Electronics Inc.,Hwaseong-si,Republic of Korea,18448"],"affiliations":[{"raw_affiliation_string":"Samsung Electronics Inc.,Hwaseong-si,Republic of Korea,18448","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100713839","display_name":"Jin\u2010Soo Park","orcid":"https://orcid.org/0000-0003-4487-946X"},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jin-Soo Park","raw_affiliation_strings":["Samsung Electronics Inc.,Hwaseong-si,Republic of Korea,18448"],"affiliations":[{"raw_affiliation_string":"Samsung Electronics Inc.,Hwaseong-si,Republic of Korea,18448","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5024804188","display_name":"Chung Hee Kim","orcid":"https://orcid.org/0000-0002-7856-3511"},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Chung-Hee Kim","raw_affiliation_strings":["Samsung Electronics Inc.,Hwaseong-si,Republic of Korea,18448"],"affiliations":[{"raw_affiliation_string":"Samsung Electronics Inc.,Hwaseong-si,Republic of Korea,18448","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5012892234","display_name":"Bai\u2010Sun Kong","orcid":"https://orcid.org/0000-0002-1077-7038"},"institutions":[{"id":"https://openalex.org/I848706","display_name":"Sungkyunkwan University","ror":"https://ror.org/04q78tk20","country_code":"KR","type":"education","lineage":["https://openalex.org/I848706"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Bai-Sun Kong","raw_affiliation_strings":["Sungkyunkwan University,The College of Information and Communication Engineering,Gyeonggi-do,Republic of Korea,16418"],"affiliations":[{"raw_affiliation_string":"Sungkyunkwan University,The College of Information and Communication Engineering,Gyeonggi-do,Republic of Korea,16418","institution_ids":["https://openalex.org/I848706"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5100343631"],"corresponding_institution_ids":["https://openalex.org/I2250650973"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.10833111,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/logic-level","display_name":"Logic level","score":0.7815275192260742},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.6815622448921204},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5377455353736877},{"id":"https://openalex.org/keywords/cascade","display_name":"Cascade","score":0.5306258201599121},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4714043140411377},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3965381979942322},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.39607661962509155},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.32219916582107544}],"concepts":[{"id":"https://openalex.org/C146569638","wikidata":"https://www.wikidata.org/wiki/Q173378","display_name":"Logic level","level":3,"score":0.7815275192260742},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.6815622448921204},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5377455353736877},{"id":"https://openalex.org/C34146451","wikidata":"https://www.wikidata.org/wiki/Q5048094","display_name":"Cascade","level":2,"score":0.5306258201599121},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4714043140411377},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3965381979942322},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.39607661962509155},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.32219916582107544},{"id":"https://openalex.org/C42360764","wikidata":"https://www.wikidata.org/wiki/Q83588","display_name":"Chemical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/socc58585.2023.10256860","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc58585.2023.10256860","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE 36th International System-on-Chip Conference (SOCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":1,"referenced_works":["https://openalex.org/W2125990238"],"related_works":["https://openalex.org/W2153719181","https://openalex.org/W1971748923","https://openalex.org/W2109445684","https://openalex.org/W2081082331","https://openalex.org/W1900707063","https://openalex.org/W3008786049","https://openalex.org/W2056291297","https://openalex.org/W2169508744","https://openalex.org/W2163294767","https://openalex.org/W1951306855"],"abstract_inverted_index":{"In":[0],"a":[1,16,20,61,89],"multiple":[2],"voltage-island":[3],"system":[4],"with":[5,70],"dynamic":[6],"voltage":[7,30,57,65,78],"scaling,":[8],"difference":[9,101],"between":[10],"rise":[11,46,72],"and":[12,47,59,73],"fall":[13,48,74],"delays":[14,49,75],"of":[15,45,50],"level":[17,52,68,83],"shifter":[18,53,69,84],"in":[19],"clock":[21],"path":[22],"can":[23],"have":[24],"large":[25],"variation":[26,44],"since":[27],"the":[28,43,51,56,99],"supply":[29],"for":[31,76],"each":[32],"island":[33],"changes":[34],"dynamically,":[35],"leading":[36],"to":[37,55,104],"performance":[38],"degradation.":[39],"This":[40],"paper":[41],"analyzes":[42],"due":[54],"change,":[58],"presents":[60],"novel":[62],"differential":[63],"cascade":[64],"switch":[66],"(DCVS)":[67],"balanced":[71],"arbitrary":[77],"conversion.":[79],"The":[80,94],"proposed":[81],"DCVS":[82],"has":[85],"been":[86],"designed":[87],"using":[88],"90nm":[90],"CMOS":[91],"process":[92],"technology.":[93],"silicon":[95],"measurement":[96],"results":[97],"indicate":[98],"maximum":[100],"decreases":[102],"up":[103],"86%.":[105]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}