{"id":"https://openalex.org/W3022332171","doi":"https://doi.org/10.1109/socc46988.2019.1570558550","title":"A 90 \u03bcW, 2.5 GHz high linearity programmable delay cell for signal duty-cycle adjustment","display_name":"A 90 \u03bcW, 2.5 GHz high linearity programmable delay cell for signal duty-cycle adjustment","publication_year":2019,"publication_date":"2019-09-01","ids":{"openalex":"https://openalex.org/W3022332171","doi":"https://doi.org/10.1109/socc46988.2019.1570558550","mag":"3022332171"},"language":"en","primary_location":{"id":"doi:10.1109/socc46988.2019.1570558550","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc46988.2019.1570558550","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5029180028","display_name":"Tobias E. Schirmer","orcid":null},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Tobias Schirmer","raw_affiliation_strings":["Technische Universität Dresden,Chair for Circuit Design and Network Theory,Germany","Chair for Circuit Design and Network Theory, Technische Universit\u00e4t Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technische Universität Dresden,Chair for Circuit Design and Network Theory,Germany","institution_ids":["https://openalex.org/I78650965"]},{"raw_affiliation_string":"Chair for Circuit Design and Network Theory, Technische Universit\u00e4t Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017988394","display_name":"Mohammad Mahdi Khafaji","orcid":"https://orcid.org/0000-0003-0044-3074"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Mohammad Mahdi Khafaji","raw_affiliation_strings":["Technische Universität Dresden,Chair for Circuit Design and Network Theory,Germany","Chair for Circuit Design and Network Theory, Technische Universit\u00e4t Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technische Universität Dresden,Chair for Circuit Design and Network Theory,Germany","institution_ids":["https://openalex.org/I78650965"]},{"raw_affiliation_string":"Chair for Circuit Design and Network Theory, Technische Universit\u00e4t Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5001786375","display_name":"Jan Pl\u00edva","orcid":null},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Jan Pliva","raw_affiliation_strings":["Technische Universität Dresden,Chair for Circuit Design and Network Theory,Germany","Chair for Circuit Design and Network Theory, Technische Universit\u00e4t Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technische Universität Dresden,Chair for Circuit Design and Network Theory,Germany","institution_ids":["https://openalex.org/I78650965"]},{"raw_affiliation_string":"Chair for Circuit Design and Network Theory, Technische Universit\u00e4t Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5049816054","display_name":"Frank Ellinger","orcid":"https://orcid.org/0000-0001-6714-0479"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Frank Ellinger","raw_affiliation_strings":["Technische Universität Dresden,Chair for Circuit Design and Network Theory,Germany","Chair for Circuit Design and Network Theory, Technische Universit\u00e4t Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technische Universität Dresden,Chair for Circuit Design and Network Theory,Germany","institution_ids":["https://openalex.org/I78650965"]},{"raw_affiliation_string":"Chair for Circuit Design and Network Theory, Technische Universit\u00e4t Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.1869545,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"278","last_page":"283"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6506933569908142},{"id":"https://openalex.org/keywords/inverter","display_name":"Inverter","score":0.5990724563598633},{"id":"https://openalex.org/keywords/linearity","display_name":"Linearity","score":0.5693328976631165},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5680515170097351},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.47125959396362305},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.39062270522117615},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3301602602005005},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.214374840259552}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6506933569908142},{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.5990724563598633},{"id":"https://openalex.org/C77170095","wikidata":"https://www.wikidata.org/wiki/Q1753188","display_name":"Linearity","level":2,"score":0.5693328976631165},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5680515170097351},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.47125959396362305},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.39062270522117615},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3301602602005005},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.214374840259552}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/socc46988.2019.1570558550","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc46988.2019.1570558550","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8700000047683716,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1533299367","https://openalex.org/W1977891801","https://openalex.org/W2072864093","https://openalex.org/W2078003863","https://openalex.org/W2099679337","https://openalex.org/W2128189348","https://openalex.org/W2336859452","https://openalex.org/W2911341463"],"related_works":["https://openalex.org/W2748952813","https://openalex.org/W3014521742","https://openalex.org/W2023858428","https://openalex.org/W98453623","https://openalex.org/W2340624421","https://openalex.org/W2113057816","https://openalex.org/W2109445684","https://openalex.org/W171113498","https://openalex.org/W2081082331","https://openalex.org/W2124661899"],"abstract_inverted_index":{"In":[0,62],"this":[1],"paper":[2],"we":[3],"introduce":[4],"the":[5,30,55,59,76,80,85,89,93,110,136,178,193,198,202],"design":[6],"of":[7,41,79,88,96,135,197],"a":[8,42,49,160,168,173,181,211],"2.5":[9],"GHz":[10],"low":[11,66,98,149],"power":[12,67,99,111,150],"CMOS":[13,44,100,161,215],"inverter":[14,45,101],"based":[15,102,121],"4-bit":[16,51],"programmable":[17],"delay":[18,46,60,90,103,127,154,199],"cell":[19,128,155],"with":[20,123,159],"high":[21],"linearity.":[22,125],"The":[23,37,126,152,204],"circuit":[24,69,187],"is":[25,74,113,144,156,206],"designed":[26],"and":[27,48,133,143,167,208],"optimized":[28],"for":[29,58,84,119,148,171],"use":[31],"in":[32,210],"high-speed":[33],"current-steering":[34],"digital-to-analog":[35,52],"converters.":[36],"basic":[38],"architecture":[39],"consists":[40],"current-starved":[43],"element":[47,200],"linear":[50],"converter":[53],"providing":[54,172],"reference":[56,130,137],"current":[57,78,131,138],"element.":[61,91],"addition,":[63],"an":[64],"analog":[65],"pre-distortion":[68,134],"has":[70,105,188],"been":[71,106,189],"implemented":[72,157,190,207],"which":[73],"modulating":[75],"output":[77],"DAC":[81],"to":[82,191],"compensate":[83],"inherent":[86],"nonlinearity":[87],"Thus,":[92],"major":[94],"drawback":[95],"state-of-the-art":[97],"elements":[104],"significantly":[107],"mitigated":[108],"whereas":[109],"consumption":[112],"still":[114],"25":[115],"times":[116],"less":[117],"than":[118],"shunt-capacitor":[120],"architectures":[122],"comparable":[124],"including":[129],"generation":[132],"only":[139],"consumes":[140],"90":[141],"\u03bcW":[142],"therefore":[145],"well":[146],"suited":[147],"applications.":[151],"proposed":[153],"along":[158],"pseudo-random":[162],"bit":[163],"sequence":[164,176],"(PRBS)":[165],"generator":[166],"retiming":[169],"flip-flop":[170],"test":[174],"data":[175],"at":[177,201],"input.":[179],"Furthermore,":[180],"50":[182],"\u03a9":[183],"impedance":[184],"matched":[185],"buffer":[186],"measure":[192],"exact":[194],"undistorted":[195],"waveforms":[196],"output.":[203],"system":[205],"fabricated":[209],"22":[212],"nm":[213],"FD-SOI":[214],"process.":[216]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}