{"id":"https://openalex.org/W2780183594","doi":"https://doi.org/10.1109/socc.2017.8226013","title":"Robust throughput boosting for low latency dynamic partial reconfiguration","display_name":"Robust throughput boosting for low latency dynamic partial reconfiguration","publication_year":2017,"publication_date":"2017-09-01","ids":{"openalex":"https://openalex.org/W2780183594","doi":"https://doi.org/10.1109/socc.2017.8226013","mag":"2780183594"},"language":"en","primary_location":{"id":"doi:10.1109/socc.2017.8226013","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2017.8226013","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://orbit.dtu.dk/en/publications/e4c5f524-52fe-4982-b644-324e8f348c8b","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5022318517","display_name":"Alberto Nannarelli","orcid":"https://orcid.org/0000-0002-8303-6329"},"institutions":[{"id":"https://openalex.org/I96673099","display_name":"Technical University of Denmark","ror":"https://ror.org/04qtj9h94","country_code":"DK","type":"education","lineage":["https://openalex.org/I96673099"]}],"countries":["DK"],"is_corresponding":true,"raw_author_name":"A. Nannarelli","raw_affiliation_strings":["DTU Compute, Technical University, Kongens Lyngby, Denmark"],"affiliations":[{"raw_affiliation_string":"DTU Compute, Technical University, Kongens Lyngby, Denmark","institution_ids":["https://openalex.org/I96673099"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000963583","display_name":"M. Re","orcid":"https://orcid.org/0000-0001-9046-1318"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M. Re","raw_affiliation_strings":["Department of Electronic Engineering, University of Rome \u201cTor Vergata\u201d, Rome, Italy","Department of Electronic Engineering, University of Rome \"Tor Vergata\", Rome, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, University of Rome \u201cTor Vergata\u201d, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]},{"raw_affiliation_string":"Department of Electronic Engineering, University of Rome \"Tor Vergata\", Rome, Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028297120","display_name":"G.C. Cardarilli","orcid":"https://orcid.org/0000-0002-7444-876X"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"G. C. Cardarilli","raw_affiliation_strings":["Department of Electronic Engineering, University of Rome \u201cTor Vergata\u201d, Rome, Italy","Department of Electronic Engineering, University of Rome \"Tor Vergata\", Rome, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, University of Rome \u201cTor Vergata\u201d, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]},{"raw_affiliation_string":"Department of Electronic Engineering, University of Rome \"Tor Vergata\", Rome, Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063300969","display_name":"Luca Di Nunzio","orcid":"https://orcid.org/0000-0002-4312-7939"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"L. Di Nunzio","raw_affiliation_strings":["Department of Electronic Engineering, University of Rome \u201cTor Vergata\u201d, Rome, Italy","Department of Electronic Engineering, University of Rome \"Tor Vergata\", Rome, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, University of Rome \u201cTor Vergata\u201d, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]},{"raw_affiliation_string":"Department of Electronic Engineering, University of Rome \"Tor Vergata\", Rome, Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043318763","display_name":"Marco Spaziani Brunella","orcid":"https://orcid.org/0000-0001-8448-0432"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M. Spaziani Brunella","raw_affiliation_strings":["Department of Electronic Engineering, University of Rome \u201cTor Vergata\u201d, Rome, Italy","Department of Electronic Engineering, University of Rome \"Tor Vergata\", Rome, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, University of Rome \u201cTor Vergata\u201d, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]},{"raw_affiliation_string":"Department of Electronic Engineering, University of Rome \"Tor Vergata\", Rome, Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048482308","display_name":"Rocco Fazzolari","orcid":"https://orcid.org/0000-0002-7383-2663"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"R. Fazzolari","raw_affiliation_strings":["Department of Electronic Engineering, University of Rome \u201cTor Vergata\u201d, Rome, Italy","Department of Electronic Engineering, University of Rome \"Tor Vergata\", Rome, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, University of Rome \u201cTor Vergata\u201d, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]},{"raw_affiliation_string":"Department of Electronic Engineering, University of Rome \"Tor Vergata\", Rome, Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5010169767","display_name":"F. Carbonari","orcid":null},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"F. Carbonari","raw_affiliation_strings":["Department of Electronic Engineering, University of Rome \u201cTor Vergata\u201d, Rome, Italy","Department of Electronic Engineering, University of Rome \"Tor Vergata\", Rome, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, University of Rome \u201cTor Vergata\u201d, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]},{"raw_affiliation_string":"Department of Electronic Engineering, University of Rome \"Tor Vergata\", Rome, Italy","institution_ids":["https://openalex.org/I116067653"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5022318517"],"corresponding_institution_ids":["https://openalex.org/I96673099"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.20145255,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"86","last_page":"90"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.9138717651367188},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8459855318069458},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7949817180633545},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.7147443294525146},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.7029442191123962},{"id":"https://openalex.org/keywords/boosting","display_name":"Boosting (machine learning)","score":0.5735626816749573},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5543859004974365},{"id":"https://openalex.org/keywords/bitstream","display_name":"Bitstream","score":0.504369854927063},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3715140223503113},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.11964258551597595},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.07833418250083923},{"id":"https://openalex.org/keywords/wireless","display_name":"Wireless","score":0.0727735161781311},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.06959238648414612},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.06465300917625427}],"concepts":[{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.9138717651367188},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8459855318069458},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7949817180633545},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.7147443294525146},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.7029442191123962},{"id":"https://openalex.org/C46686674","wikidata":"https://www.wikidata.org/wiki/Q466303","display_name":"Boosting (machine learning)","level":2,"score":0.5735626816749573},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5543859004974365},{"id":"https://openalex.org/C136695289","wikidata":"https://www.wikidata.org/wiki/Q415568","display_name":"Bitstream","level":3,"score":0.504369854927063},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3715140223503113},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.11964258551597595},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.07833418250083923},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0727735161781311},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.06959238648414612},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.06465300917625427},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/socc.2017.8226013","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2017.8226013","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","raw_type":"proceedings-article"},{"id":"pmh:oai:art.torvergata.it:2108/238577","is_oa":false,"landing_page_url":"http://hdl.handle.net/2108/238577","pdf_url":null,"source":{"id":"https://openalex.org/S4306400993","display_name":"Cineca Institutional Research Information System (Tor Vergata University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I116067653","host_organization_name":"University of Rome Tor Vergata","host_organization_lineage":["https://openalex.org/I116067653"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"},{"id":"pmh:oai:pure.atira.dk:publications/e4c5f524-52fe-4982-b644-324e8f348c8b","is_oa":true,"landing_page_url":"https://orbit.dtu.dk/en/publications/e4c5f524-52fe-4982-b644-324e8f348c8b","pdf_url":null,"source":{"id":"https://openalex.org/S4306400705","display_name":"Technical University of Denmark, DTU Orbit (Technical University of Denmark, DTU)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I96673099","host_organization_name":"Technical University of Denmark","host_organization_lineage":["https://openalex.org/I96673099"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Nannarelli , A , Re , M , Cardarilli , G C , Nunzio , L D , Brunella , M S , Fazzolari , R & Carbonari , F 2017 , Robust Throughput Boosting for Low Latency Dynamic Partial Reconfiguration . in Proceedins of the 30th IEEE International System-on-Chip Conference . IEEE , pp. 86-90 , 2017 30th IEEE International System-on-Chip Conference , M\u00fcnchen , Bavaria , Germany , 05/09/2017 .","raw_type":"contributionToPeriodical"}],"best_oa_location":{"id":"pmh:oai:pure.atira.dk:publications/e4c5f524-52fe-4982-b644-324e8f348c8b","is_oa":true,"landing_page_url":"https://orbit.dtu.dk/en/publications/e4c5f524-52fe-4982-b644-324e8f348c8b","pdf_url":null,"source":{"id":"https://openalex.org/S4306400705","display_name":"Technical University of Denmark, DTU Orbit (Technical University of Denmark, DTU)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I96673099","host_organization_name":"Technical University of Denmark","host_organization_lineage":["https://openalex.org/I96673099"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Nannarelli , A , Re , M , Cardarilli , G C , Nunzio , L D , Brunella , M S , Fazzolari , R & Carbonari , F 2017 , Robust Throughput Boosting for Low Latency Dynamic Partial Reconfiguration . in Proceedins of the 30th IEEE International System-on-Chip Conference . IEEE , pp. 86-90 , 2017 30th IEEE International System-on-Chip Conference , M\u00fcnchen , Bavaria , Germany , 05/09/2017 .","raw_type":"contributionToPeriodical"},"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.7300000190734863,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1764493129","https://openalex.org/W2018817973","https://openalex.org/W2080556528","https://openalex.org/W2095858451","https://openalex.org/W2149611663","https://openalex.org/W2154363663","https://openalex.org/W2158203472","https://openalex.org/W2580284127","https://openalex.org/W2583383421"],"related_works":["https://openalex.org/W2808484818","https://openalex.org/W2810427553","https://openalex.org/W4319430423","https://openalex.org/W2135053878","https://openalex.org/W2941434274","https://openalex.org/W4390224957","https://openalex.org/W2340647897","https://openalex.org/W4249632163","https://openalex.org/W1760305469","https://openalex.org/W2797161794"],"abstract_inverted_index":{"Reducing":[0],"the":[1,27,45,50,54,65,98,107],"configuration":[2,46,81],"time":[3,11],"of":[4,6,56,74,83,89,112],"portions":[5],"an":[7],"FPGA":[8,30],"at":[9],"run":[10],"is":[12,41],"crucial":[13],"in":[14,53],"contemporary":[15],"FPGA-based":[16,113],"accelerators.":[17,114],"In":[18],"this":[19],"work,":[20],"we":[21],"propose":[22],"a":[23,72,80,103],"method":[24],"to":[25,79,96,105],"increase":[26],"throughput":[28,40,73,100],"for":[29,87],"dynamic":[31],"partial":[32],"reconfiguration":[33,99],"by":[34,43],"using":[35],"standard":[36,58],"IP":[37],"blocks.":[38,59],"The":[39,60],"increased":[42],"over-clocking":[44],"bitstream":[47],"circuitry":[48],"beyond":[49],"limits":[51],"stated":[52],"specifications":[55],"these":[57],"experimental":[61],"results":[62],"show":[63],"that":[64],"most":[66,108],"power":[67,109],"efficient":[68,110],"implementation":[69,111],"can":[70],"reach":[71],"about":[75,84],"780":[76],"MB/s,":[77],"corresponding":[78],"latency":[82],"670":[85],"micro-seconds":[86],"bitstreams":[88],"1.2":[90],"MB.":[91],"We":[92],"also":[93],"investigate":[94],"alternatives":[95],"boost":[97],"and":[101],"sketch":[102],"methodology":[104],"achieve":[106]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1}],"updated_date":"2026-02-25T23:00:34.991745","created_date":"2018-01-05T00:00:00"}