{"id":"https://openalex.org/W2607590752","doi":"https://doi.org/10.1109/socc.2016.7905427","title":"Low-jitter all-digital phase-locked loop with novel PFD and high resolution TDC & DCO","display_name":"Low-jitter all-digital phase-locked loop with novel PFD and high resolution TDC & DCO","publication_year":2016,"publication_date":"2016-09-01","ids":{"openalex":"https://openalex.org/W2607590752","doi":"https://doi.org/10.1109/socc.2016.7905427","mag":"2607590752"},"language":"en","primary_location":{"id":"doi:10.1109/socc.2016.7905427","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2016.7905427","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 29th IEEE International System-on-Chip Conference (SOCC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5047805277","display_name":"Xiaoying Deng","orcid":"https://orcid.org/0000-0002-7423-8535"},"institutions":[{"id":"https://openalex.org/I180726961","display_name":"Shenzhen University","ror":"https://ror.org/01vy4gh70","country_code":"CN","type":"education","lineage":["https://openalex.org/I180726961"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Xiaoying Deng","raw_affiliation_strings":["College of Information Engineering, Shenzhen University, Shenzhen, China"],"affiliations":[{"raw_affiliation_string":"College of Information Engineering, Shenzhen University, Shenzhen, China","institution_ids":["https://openalex.org/I180726961"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074562034","display_name":"Yanyan Mo","orcid":null},"institutions":[{"id":"https://openalex.org/I180726961","display_name":"Shenzhen University","ror":"https://ror.org/01vy4gh70","country_code":"CN","type":"education","lineage":["https://openalex.org/I180726961"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yanyan Mo","raw_affiliation_strings":["College of Information Engineering, Shenzhen University, Shenzhen, China"],"affiliations":[{"raw_affiliation_string":"College of Information Engineering, Shenzhen University, Shenzhen, China","institution_ids":["https://openalex.org/I180726961"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102213605","display_name":"Xin Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I180726961","display_name":"Shenzhen University","ror":"https://ror.org/01vy4gh70","country_code":"CN","type":"education","lineage":["https://openalex.org/I180726961"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xin Lin","raw_affiliation_strings":["College of Information Engineering, Shenzhen University, Shenzhen, China"],"affiliations":[{"raw_affiliation_string":"College of Information Engineering, Shenzhen University, Shenzhen, China","institution_ids":["https://openalex.org/I180726961"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100612417","display_name":"Mingcheng Zhu","orcid":"https://orcid.org/0000-0001-8771-6914"},"institutions":[{"id":"https://openalex.org/I180726961","display_name":"Shenzhen University","ror":"https://ror.org/01vy4gh70","country_code":"CN","type":"education","lineage":["https://openalex.org/I180726961"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Mingcheng Zhu","raw_affiliation_strings":["College of Information Engineering, Shenzhen University, Shenzhen, China"],"affiliations":[{"raw_affiliation_string":"College of Information Engineering, Shenzhen University, Shenzhen, China","institution_ids":["https://openalex.org/I180726961"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5047805277"],"corresponding_institution_ids":["https://openalex.org/I180726961"],"apc_list":null,"apc_paid":null,"fwci":0.3675,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.68483687,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"29","last_page":"34"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11429","display_name":"Semiconductor Lasers and Optical Devices","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9959999918937683,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.9147180318832397},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.5758793950080872},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5377625823020935},{"id":"https://openalex.org/keywords/time-to-digital-converter","display_name":"Time-to-digital converter","score":0.4366917014122009},{"id":"https://openalex.org/keywords/amplifier","display_name":"Amplifier","score":0.4284396171569824},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.42837095260620117},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.3871704339981079},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12254124879837036},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.12225651741027832}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.9147180318832397},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.5758793950080872},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5377625823020935},{"id":"https://openalex.org/C99594498","wikidata":"https://www.wikidata.org/wiki/Q2434524","display_name":"Time-to-digital converter","level":4,"score":0.4366917014122009},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.4284396171569824},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.42837095260620117},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.3871704339981079},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12254124879837036},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.12225651741027832}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/socc.2016.7905427","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2016.7905427","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 29th IEEE International System-on-Chip Conference (SOCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8999999761581421,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1975693956","https://openalex.org/W2021980694","https://openalex.org/W2067333289","https://openalex.org/W2068786231","https://openalex.org/W2111018235","https://openalex.org/W2120935131"],"related_works":["https://openalex.org/W2121182846","https://openalex.org/W2315668284","https://openalex.org/W2155789024","https://openalex.org/W2109491806","https://openalex.org/W3213608175","https://openalex.org/W2058044441","https://openalex.org/W3117675750","https://openalex.org/W2139484866","https://openalex.org/W2036880312","https://openalex.org/W2128081842"],"abstract_inverted_index":{"A":[0,52],"low-jitter":[1],"and":[2,39,49,66,109,114,144],"wide":[3,45],"output":[4,85,103,146],"frequency":[5,46,86,104,147],"range":[6,48,70],"ADPLL":[7,76,89,136],"was":[8,57,77],"proposed":[9,75,131,135],"in":[10,79,139],"this":[11],"paper.":[12],"The":[13,27,74,84,117],"adopted":[14],"PFD":[15],"based":[16,54],"on":[17],"sense-amplifier":[18],"flip-flop":[19],"(SAFF)":[20],"can":[21],"effectively":[22],"improve":[23],"the":[24,88,102,107,129,134],"jitter":[25,143],"performance.":[26],"novel":[28],"DCO":[29],"with":[30,60,96],"cascading":[31],"structure":[32],"consists":[33],"of":[34,64,71,87],"a":[35,40,61,67,97],"coarse-tuning":[36],"delay":[37],"chain":[38],"fine-tuning":[41],"interpolator,":[42],"obtaining":[43],"both":[44],"tuning":[47],"high":[50],"resolution.":[51],"time-amplifier":[53],"sub-exponent":[55],"TDC":[56],"also":[58],"designed":[59,78],"minimum":[62],"resolution":[63],"1.25ps":[65],"total":[68],"conversion":[69],"2.5":[72],"ns.":[73],"SMIC":[80],"0.18\u03bcm":[81],"CMOS":[82],"process.":[83],"ranges":[90],"from":[91],"0.64":[92],"to":[93,128],"1.44":[94],"GHz":[95],"40MHz":[98],"reference":[99],"frequency.":[100],"When":[101],"is":[105,121],"1.28GHz,":[106],"peak-to-peak":[108],"rms":[110],"jitters":[111],"are":[112],"22.3ps":[113],"2.1ps":[115],"respectively.":[116],"maximum":[118],"power":[119],"consumption":[120],"24.43mW":[122],"at":[123],"(1.8v,":[124],"1.44GHz).":[125],"With":[126],"respect":[127],"recently":[130],"high-performance":[132],"ADPLLs,":[133],"shows":[137],"advantages":[138],"smaller":[140],"area,":[141],"lower":[142],"wider":[145],"range.":[148]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}