{"id":"https://openalex.org/W2288889051","doi":"https://doi.org/10.1109/socc.2015.7406981","title":"The evolutionary spintronic technologies and their usage in high performance computing","display_name":"The evolutionary spintronic technologies and their usage in high performance computing","publication_year":2015,"publication_date":"2015-09-01","ids":{"openalex":"https://openalex.org/W2288889051","doi":"https://doi.org/10.1109/socc.2015.7406981","mag":"2288889051"},"language":"en","primary_location":{"id":"doi:10.1109/socc.2015.7406981","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2015.7406981","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100429403","display_name":"Hai Li","orcid":"https://orcid.org/0000-0003-3228-6544"},"institutions":[{"id":"https://openalex.org/I170201317","display_name":"University of Pittsburgh","ror":"https://ror.org/01an3r305","country_code":"US","type":"education","lineage":["https://openalex.org/I170201317"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hai Helen Li","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Pittsburgh, Pennsylvania, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Pittsburgh, Pennsylvania, USA","institution_ids":["https://openalex.org/I170201317"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066400911","display_name":"Xiuyuan Bi","orcid":"https://orcid.org/0000-0002-7401-6764"},"institutions":[{"id":"https://openalex.org/I170201317","display_name":"University of Pittsburgh","ror":"https://ror.org/01an3r305","country_code":"US","type":"education","lineage":["https://openalex.org/I170201317"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xiuyuan Bi","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Pittsburgh, Pennsylvania, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Pittsburgh, Pennsylvania, USA","institution_ids":["https://openalex.org/I170201317"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103258530","display_name":"Zhenyu Sun","orcid":"https://orcid.org/0000-0002-6584-3629"},"institutions":[{"id":"https://openalex.org/I170201317","display_name":"University of Pittsburgh","ror":"https://ror.org/01an3r305","country_code":"US","type":"education","lineage":["https://openalex.org/I170201317"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zhenyu Sun","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Pittsburgh, Pennsylvania, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Pittsburgh, Pennsylvania, USA","institution_ids":["https://openalex.org/I170201317"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I170201317"],"apc_list":null,"apc_paid":null,"fwci":0.2177,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.6227586,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"350","last_page":"355"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10049","display_name":"Magnetic properties of thin films","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/3107","display_name":"Atomic and Molecular Physics, and Optics"},"field":{"id":"https://openalex.org/fields/31","display_name":"Physics and Astronomy"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10049","display_name":"Magnetic properties of thin films","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/3107","display_name":"Atomic and Molecular Physics, and Optics"},"field":{"id":"https://openalex.org/fields/31","display_name":"Physics and Astronomy"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7762032747268677},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5737511515617371},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.5068517327308655},{"id":"https://openalex.org/keywords/performance-improvement","display_name":"Performance improvement","score":0.48647400736808777},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.42796045541763306},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4189970791339874},{"id":"https://openalex.org/keywords/racetrack-memory","display_name":"Racetrack memory","score":0.4100780785083771},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3941706717014313},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.3143855333328247},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.2727707624435425},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.26710057258605957},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.22530922293663025},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.0950162410736084}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7762032747268677},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5737511515617371},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.5068517327308655},{"id":"https://openalex.org/C2778915421","wikidata":"https://www.wikidata.org/wiki/Q3643177","display_name":"Performance improvement","level":2,"score":0.48647400736808777},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.42796045541763306},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4189970791339874},{"id":"https://openalex.org/C43363307","wikidata":"https://www.wikidata.org/wiki/Q1651623","display_name":"Racetrack memory","level":5,"score":0.4100780785083771},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3941706717014313},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.3143855333328247},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.2727707624435425},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.26710057258605957},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.22530922293663025},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0950162410736084},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/socc.2015.7406981","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2015.7406981","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W1978085294","https://openalex.org/W1980034734","https://openalex.org/W1994569665","https://openalex.org/W2000818868","https://openalex.org/W2001641336","https://openalex.org/W2005242923","https://openalex.org/W2010202670","https://openalex.org/W2012025286","https://openalex.org/W2017836239","https://openalex.org/W2029083842","https://openalex.org/W2053331999","https://openalex.org/W2078760460","https://openalex.org/W2101717804","https://openalex.org/W2102840382","https://openalex.org/W2108048675","https://openalex.org/W2116344741","https://openalex.org/W2120246901","https://openalex.org/W2120699192","https://openalex.org/W2151805400","https://openalex.org/W2156728623","https://openalex.org/W2165291203","https://openalex.org/W2171779727","https://openalex.org/W2543205889","https://openalex.org/W3144904247","https://openalex.org/W4238440425","https://openalex.org/W6655050512","https://openalex.org/W6677325608"],"related_works":["https://openalex.org/W1993178305","https://openalex.org/W776329307","https://openalex.org/W1989028197","https://openalex.org/W2473964774","https://openalex.org/W2543577874","https://openalex.org/W2315140189","https://openalex.org/W2505369450","https://openalex.org/W3134061447","https://openalex.org/W2116344741","https://openalex.org/W4232132130"],"abstract_inverted_index":{"This":[0,105],"paper":[1,106],"gives":[2],"a":[3,129],"comprehensive":[4],"summary":[5],"of":[6,20,39,41,144,147],"our":[7,109],"study":[8],"in":[9,80,101],"using":[10],"the":[11,15,29,37,48,69,74,85,89,142],"spintronic":[12,116],"technologies":[13],"for":[14],"on-chip":[16],"cache":[17],"density":[18,86,126],"improvement":[19],"high":[21,124],"performance":[22,103],"computing":[23],"systems.":[24],"We":[25],"will":[26,107],"start":[27],"with":[28],"spin-transfer":[30],"torque":[31],"random":[32],"access":[33],"memory":[34,51,136],"(STT-RAM)":[35],"at":[36,57],"early":[38],"stage":[40],"commercialization":[42],"and":[43,59,78,93,111,127],"then":[44],"extend":[45],"it":[46],"to":[47,140],"emerging":[49],"racetrack":[50,119,148],"that":[52],"has":[53],"been":[54],"successfully":[55],"demonstrated":[56],"device":[58],"small":[60],"array":[61],"level.":[62],"In":[63],"multi-level":[64],"cell":[65,70],"(MLC)":[66],"STT-RAM":[67],"cache,":[68],"design":[71],"constrains,":[72],"e.g.,":[73],"switching":[75],"current":[76],"requirement":[77],"asymmetry":[79],"write":[81],"operations,":[82],"severely":[83],"limit":[84],"benefit.":[87],"Moreover,":[88],"two-step":[90],"read/write":[91],"accesses":[92,146],"inflexible":[94],"data":[95],"mapping":[96],"strategy":[97],"may":[98],"even":[99],"result":[100],"system":[102],"degradation.":[104],"discuss":[108],"circuit":[110],"architecture":[112],"combined":[113],"solution.":[114],"Advanced":[115],"technology,":[117],"i.e.,":[118],"memory,":[120],"enables":[121],"an":[122],"extremely":[123],"storage":[125],"offers":[128],"faster-than-Moores":[130],"law":[131],"scaling":[132],"path.":[133],"Unorthodox":[134],"new":[135],"hierarchies":[137],"are":[138],"necessary":[139],"minimize":[141],"impact":[143],"pseudo-sequential":[145],"memory.":[149]},"counts_by_year":[{"year":2016,"cited_by_count":1}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}
