{"id":"https://openalex.org/W2291056456","doi":"https://doi.org/10.1109/socc.2015.7406952","title":"A digital background calibration technique for split DAC based SAR ADC by using redundant cycle","display_name":"A digital background calibration technique for split DAC based SAR ADC by using redundant cycle","publication_year":2015,"publication_date":"2015-09-01","ids":{"openalex":"https://openalex.org/W2291056456","doi":"https://doi.org/10.1109/socc.2015.7406952","mag":"2291056456"},"language":"en","primary_location":{"id":"doi:10.1109/socc.2015.7406952","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2015.7406952","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5059222566","display_name":"Wuguang Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I4210092088","display_name":"Zhejiang Province Institute of Architectural Design and Research","ror":"https://ror.org/00f89ms08","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210092088"]},{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Wuguang Wang","raw_affiliation_strings":["Institute of VLSI Design, Zhejiang University, Hangzhou, P. R. China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of VLSI Design, Zhejiang University, Hangzhou, P. R. China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101987657","display_name":"Rulin Huang","orcid":"https://orcid.org/0000-0003-1347-892X"},"institutions":[{"id":"https://openalex.org/I4210092088","display_name":"Zhejiang Province Institute of Architectural Design and Research","ror":"https://ror.org/00f89ms08","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210092088"]},{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Rulin Huang","raw_affiliation_strings":["Institute of VLSI Design, Zhejiang University, Hangzhou, P. R. China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of VLSI Design, Zhejiang University, Hangzhou, P. R. China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101146203","display_name":"Guo\u2010Quan Sun","orcid":"https://orcid.org/0000-0001-7912-672X"},"institutions":[{"id":"https://openalex.org/I4210092088","display_name":"Zhejiang Province Institute of Architectural Design and Research","ror":"https://ror.org/00f89ms08","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210092088"]},{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Guoquan Sun","raw_affiliation_strings":["Institute of VLSI Design, Zhejiang University, Hangzhou, P. R. China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of VLSI Design, Zhejiang University, Hangzhou, P. R. China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102183292","display_name":"Mao Weijun","orcid":null},"institutions":[{"id":"https://openalex.org/I4210092088","display_name":"Zhejiang Province Institute of Architectural Design and Research","ror":"https://ror.org/00f89ms08","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210092088"]},{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Weijun Mao","raw_affiliation_strings":["Institute of VLSI Design, Zhejiang University, Hangzhou, P. R. China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of VLSI Design, Zhejiang University, Hangzhou, P. R. China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5027236515","display_name":"Xiaolei Zhu","orcid":"https://orcid.org/0000-0001-8141-021X"},"institutions":[{"id":"https://openalex.org/I4210092088","display_name":"Zhejiang Province Institute of Architectural Design and Research","ror":"https://ror.org/00f89ms08","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210092088"]},{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaolei Zhu","raw_affiliation_strings":["Institute of VLSI Design, Zhejiang University, Hangzhou, P. R. China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of VLSI Design, Zhejiang University, Hangzhou, P. R. China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.24508201,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"231","last_page":"234"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11472","display_name":"Analytical Chemistry and Sensors","score":0.9950000047683716,"subfield":{"id":"https://openalex.org/subfields/1502","display_name":"Bioengineering"},"field":{"id":"https://openalex.org/fields/15","display_name":"Chemical Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/calibration","display_name":"Calibration","score":0.7568314075469971},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.7407069802284241},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7037813067436218},{"id":"https://openalex.org/keywords/successive-approximation-adc","display_name":"Successive approximation ADC","score":0.5445459485054016},{"id":"https://openalex.org/keywords/least-significant-bit","display_name":"Least significant bit","score":0.5348085165023804},{"id":"https://openalex.org/keywords/12-bit","display_name":"12-bit","score":0.4916272759437561},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.48205217719078064},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.46576666831970215},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.40436941385269165},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.21137896180152893},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.192253977060318},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.174606055021286},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16564291715621948},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1031392514705658}],"concepts":[{"id":"https://openalex.org/C165838908","wikidata":"https://www.wikidata.org/wiki/Q736777","display_name":"Calibration","level":2,"score":0.7568314075469971},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.7407069802284241},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7037813067436218},{"id":"https://openalex.org/C60154766","wikidata":"https://www.wikidata.org/wiki/Q2650458","display_name":"Successive approximation ADC","level":4,"score":0.5445459485054016},{"id":"https://openalex.org/C4305246","wikidata":"https://www.wikidata.org/wiki/Q3885225","display_name":"Least significant bit","level":2,"score":0.5348085165023804},{"id":"https://openalex.org/C2776310492","wikidata":"https://www.wikidata.org/wiki/Q3271420","display_name":"12-bit","level":3,"score":0.4916272759437561},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.48205217719078064},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.46576666831970215},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.40436941385269165},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.21137896180152893},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.192253977060318},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.174606055021286},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16564291715621948},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1031392514705658},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/socc.2015.7406952","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2015.7406952","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.699999988079071}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1980893811","https://openalex.org/W1995648121","https://openalex.org/W1999118881","https://openalex.org/W2038370925","https://openalex.org/W2071366656","https://openalex.org/W2078717740","https://openalex.org/W2093607504","https://openalex.org/W6645543914","https://openalex.org/W6680844038"],"related_works":["https://openalex.org/W2109469245","https://openalex.org/W3080615287","https://openalex.org/W2488845768","https://openalex.org/W2805237214","https://openalex.org/W2028124978","https://openalex.org/W2008952700","https://openalex.org/W2593068112","https://openalex.org/W2805845672","https://openalex.org/W2915814539","https://openalex.org/W3128305238"],"abstract_inverted_index":{"A":[0,41],"digital":[1],"background":[2],"calibration":[3,20,32,77],"technique":[4],"for":[5],"split":[6],"CDAC":[7,26],"mismatch":[8,23],"is":[9,28,46],"proposed.":[10],"It":[11],"uses":[12],"the":[13,25,31,38,57],"dummy":[14],"capacitor":[15],"to":[16,37,64],"generate":[17],"an":[18],"extra":[19],"bit.":[21],"The":[22,75],"of":[24],"array":[27],"detected":[29],"by":[30],"bit":[33],"and":[34,59,67],"fed":[35],"back":[36],"compensation":[39],"capacitor.":[40],"9b":[42],"100MS/s":[43],"SAR":[44],"ADC":[45],"demonstrated":[47],"in":[48],"standard":[49],"65nm":[50],"CMOS":[51],"technology.":[52],"Simulation":[53],"results":[54],"show":[55],"that":[56],"DNL":[58],"INL":[60],"can":[61],"be":[62],"decreased":[63],"\u00b10.1":[65],"LSB":[66],"+0.11/-0.13":[68],"LSB,":[69],"respectively,":[70],"after":[71],"using":[72],"this":[73],"technique.":[74],"proposed":[76],"block":[78],"consumes":[79],"only":[80],"50\u03bcw":[81],"from":[82],"a":[83],"1.2V":[84],"supply.":[85]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}