{"id":"https://openalex.org/W2072317809","doi":"https://doi.org/10.1109/socc.2014.6948969","title":"A hardware acceleration scheme for memory-efficient flow processing","display_name":"A hardware acceleration scheme for memory-efficient flow processing","publication_year":2014,"publication_date":"2014-09-01","ids":{"openalex":"https://openalex.org/W2072317809","doi":"https://doi.org/10.1109/socc.2014.6948969","mag":"2072317809"},"language":"en","primary_location":{"id":"doi:10.1109/socc.2014.6948969","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2014.6948969","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 27th IEEE International System-on-Chip Conference (SOCC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://pureadmin.qub.ac.uk/ws/files/18189706/54_Paper.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100719715","display_name":"Xin Yang","orcid":"https://orcid.org/0000-0003-3428-3806"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Xin Yang","raw_affiliation_strings":["ECIT Institute, Queen's University Belfast, Northern, Ireland","ECIT Institute, Queen's University Belfast, Northern Ireland"],"affiliations":[{"raw_affiliation_string":"ECIT Institute, Queen's University Belfast, Northern, Ireland","institution_ids":[]},{"raw_affiliation_string":"ECIT Institute, Queen's University Belfast, Northern Ireland","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103745938","display_name":"Sakir Sezer","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Sakir Sezer","raw_affiliation_strings":["ECIT Institute, Queen's University Belfast, Northern, Ireland","ECIT Institute, Queen's University Belfast, Northern Ireland"],"affiliations":[{"raw_affiliation_string":"ECIT Institute, Queen's University Belfast, Northern, Ireland","institution_ids":[]},{"raw_affiliation_string":"ECIT Institute, Queen's University Belfast, Northern Ireland","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102129489","display_name":"Shane O\u2019Neill","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Shane O'Neill","raw_affiliation_strings":["ECIT Institute, Queen's University Belfast, Northern, Ireland","ECIT Institute, Queen's University Belfast, Northern Ireland"],"affiliations":[{"raw_affiliation_string":"ECIT Institute, Queen's University Belfast, Northern, Ireland","institution_ids":[]},{"raw_affiliation_string":"ECIT Institute, Queen's University Belfast, Northern Ireland","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5100719715"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.316,"has_fulltext":true,"cited_by_count":1,"citation_normalized_percentile":{"value":0.61102023,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"4","issue":null,"first_page":"437","last_page":"442"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11478","display_name":"Caching and Content Delivery","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10138","display_name":"Network Traffic and Congestion Control","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7624019384384155},{"id":"https://openalex.org/keywords/packet-processing","display_name":"Packet processing","score":0.7326837182044983},{"id":"https://openalex.org/keywords/network-processor","display_name":"Network processor","score":0.6842703819274902},{"id":"https://openalex.org/keywords/header","display_name":"Header","score":0.635535478591919},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.6160584688186646},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.589438259601593},{"id":"https://openalex.org/keywords/ethernet","display_name":"Ethernet","score":0.5764036774635315},{"id":"https://openalex.org/keywords/network-packet","display_name":"Network packet","score":0.520717442035675},{"id":"https://openalex.org/keywords/hardware-acceleration","display_name":"Hardware acceleration","score":0.4650036096572876},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.46456968784332275},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.41925036907196045},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3982885181903839},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.23054906725883484}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7624019384384155},{"id":"https://openalex.org/C2779581428","wikidata":"https://www.wikidata.org/wiki/Q7122997","display_name":"Packet processing","level":3,"score":0.7326837182044983},{"id":"https://openalex.org/C74366991","wikidata":"https://www.wikidata.org/wiki/Q2755335","display_name":"Network processor","level":3,"score":0.6842703819274902},{"id":"https://openalex.org/C48105269","wikidata":"https://www.wikidata.org/wiki/Q1141160","display_name":"Header","level":2,"score":0.635535478591919},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.6160584688186646},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.589438259601593},{"id":"https://openalex.org/C172173386","wikidata":"https://www.wikidata.org/wiki/Q79984","display_name":"Ethernet","level":2,"score":0.5764036774635315},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.520717442035675},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.4650036096572876},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.46456968784332275},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.41925036907196045},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3982885181903839},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.23054906725883484},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/socc.2014.6948969","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2014.6948969","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 27th IEEE International System-on-Chip Conference (SOCC)","raw_type":"proceedings-article"},{"id":"pmh:oai:pure.qub.ac.uk/portal:openaire/56a75a43-0d6f-40c8-b6da-ccaf95a26f3b","is_oa":true,"landing_page_url":"https://pure.qub.ac.uk/en/publications/56a75a43-0d6f-40c8-b6da-ccaf95a26f3b","pdf_url":"https://pureadmin.qub.ac.uk/ws/files/18189706/54_Paper.pdf","source":{"id":"https://openalex.org/S4306402319","display_name":"Research Portal (Queen's University Belfast)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I126231945","host_organization_name":"Queen's University Belfast","host_organization_lineage":["https://openalex.org/I126231945"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Yang, X, Sezer, S & O'Neill, S 2014, A Hardware Acceleration Scheme for Memory-Efficient Flow Processing. in 2014 27th IEEE International System-on-Chip Conference (SOCC). Institute of Electrical and Electronics Engineers Inc., pp. 437-442, IEEE System-on-Chip Conference (SOCC) , Las Vegas, United States, 02/09/2014. https://doi.org/10.1109/SOCC.2014.6948969","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":{"id":"pmh:oai:pure.qub.ac.uk/portal:openaire/56a75a43-0d6f-40c8-b6da-ccaf95a26f3b","is_oa":true,"landing_page_url":"https://pure.qub.ac.uk/en/publications/56a75a43-0d6f-40c8-b6da-ccaf95a26f3b","pdf_url":"https://pureadmin.qub.ac.uk/ws/files/18189706/54_Paper.pdf","source":{"id":"https://openalex.org/S4306402319","display_name":"Research Portal (Queen's University Belfast)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I126231945","host_organization_name":"Queen's University Belfast","host_organization_lineage":["https://openalex.org/I126231945"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Yang, X, Sezer, S & O'Neill, S 2014, A Hardware Acceleration Scheme for Memory-Efficient Flow Processing. in 2014 27th IEEE International System-on-Chip Conference (SOCC). Institute of Electrical and Electronics Engineers Inc., pp. 437-442, IEEE System-on-Chip Conference (SOCC) , Las Vegas, United States, 02/09/2014. https://doi.org/10.1109/SOCC.2014.6948969","raw_type":"info:eu-repo/semantics/conferenceObject"},"sustainable_development_goals":[{"score":0.5199999809265137,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[{"id":"https://openalex.org/G5334834590","display_name":null,"funder_award_id":"EP/H049606/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G5445011987","display_name":null,"funder_award_id":"EP/K004379/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G745166385","display_name":null,"funder_award_id":"EP/G034303/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G7778643072","display_name":null,"funder_award_id":"EP/J006238/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"}],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2072317809.pdf","grobid_xml":"https://content.openalex.org/works/W2072317809.grobid-xml"},"referenced_works_count":12,"referenced_works":["https://openalex.org/W1980088630","https://openalex.org/W1993284846","https://openalex.org/W2037441202","https://openalex.org/W2092878677","https://openalex.org/W2103130144","https://openalex.org/W2113243322","https://openalex.org/W2113374088","https://openalex.org/W2116967744","https://openalex.org/W2157216338","https://openalex.org/W2912437396","https://openalex.org/W6675512943","https://openalex.org/W6758302342"],"related_works":["https://openalex.org/W2060889682","https://openalex.org/W1606574587","https://openalex.org/W1556003661","https://openalex.org/W1233822343","https://openalex.org/W2097595905","https://openalex.org/W4235315652","https://openalex.org/W2390663577","https://openalex.org/W1993620881","https://openalex.org/W2097731574","https://openalex.org/W2154462221"],"abstract_inverted_index":{"This":[0,74],"paper":[1],"presents":[2],"a":[3,66],"hardware":[4],"solution":[5],"for":[6,45,54],"network":[7],"flow":[8,26,46],"processing":[9],"at":[10,82],"full":[11],"line":[12],"rate.":[13],"Advanced":[14],"memory":[15],"architecture":[16,50],"using":[17],"DDR3":[18],"SDRAMs":[19],"is":[20,75],"proposed":[21],"to":[22,77],"cope":[23],"with":[24],"the":[25],"match":[27],"limitations":[28],"in":[29],"packet":[30,39],"throughput,":[31],"number":[32,37],"of":[33,38,68],"supported":[34,44],"flows":[35,81],"and":[36,59],"header":[40],"fields":[41],"(or":[42],"tuples)":[43],"identifications.":[47],"The":[48],"described":[49],"has":[51],"been":[52],"prototyped":[53],"accommodating":[55],"8":[56],"million":[57,70],"flows,":[58],"tested":[60],"on":[61],"an":[62],"FPGA":[63],"platform":[64],"achieving":[65],"minimum":[67],"70":[69],"lookups":[71],"per":[72],"second.":[73],"sufficient":[76],"process":[78],"internet":[79],"traffic":[80],"40":[83],"Gigabit":[84],"Ethernet.":[85]},"counts_by_year":[{"year":2015,"cited_by_count":1}],"updated_date":"2026-03-17T09:09:15.849793","created_date":"2025-10-10T00:00:00"}
