{"id":"https://openalex.org/W2041204497","doi":"https://doi.org/10.1109/socc.2014.6948939","title":"A framework for specifying, modeling, implementation and verification of SOC protocols","display_name":"A framework for specifying, modeling, implementation and verification of SOC protocols","publication_year":2014,"publication_date":"2014-09-01","ids":{"openalex":"https://openalex.org/W2041204497","doi":"https://doi.org/10.1109/socc.2014.6948939","mag":"2041204497"},"language":"en","primary_location":{"id":"doi:10.1109/socc.2014.6948939","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2014.6948939","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 27th IEEE International System-on-Chip Conference (SOCC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014045053","display_name":"Shahid Ikram","orcid":null},"institutions":[{"id":"https://openalex.org/I4210095037","display_name":"Cavium (United States)","ror":"https://ror.org/00qbcq685","country_code":"US","type":"company","lineage":["https://openalex.org/I4210095037"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Shahid Ikram","raw_affiliation_strings":["Cavium Networks, Marlborough, MA","Cavium Networks, 600 Nickerson Road, Marlborough, MA 01751, USA"],"affiliations":[{"raw_affiliation_string":"Cavium Networks, Marlborough, MA","institution_ids":["https://openalex.org/I4210095037"]},{"raw_affiliation_string":"Cavium Networks, 600 Nickerson Road, Marlborough, MA 01751, USA","institution_ids":["https://openalex.org/I4210095037"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078841733","display_name":"David J. Asher","orcid":null},"institutions":[{"id":"https://openalex.org/I4210095037","display_name":"Cavium (United States)","ror":"https://ror.org/00qbcq685","country_code":"US","type":"company","lineage":["https://openalex.org/I4210095037"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David Asher","raw_affiliation_strings":["Cavium Networks, San Jose, CA","Cavium Networks, 600 Nickerson Road, Marlborough, MA 01751, USA"],"affiliations":[{"raw_affiliation_string":"Cavium Networks, San Jose, CA","institution_ids":["https://openalex.org/I4210095037"]},{"raw_affiliation_string":"Cavium Networks, 600 Nickerson Road, Marlborough, MA 01751, USA","institution_ids":["https://openalex.org/I4210095037"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075502330","display_name":"Isam Akkawi","orcid":null},"institutions":[{"id":"https://openalex.org/I4210095037","display_name":"Cavium (United States)","ror":"https://ror.org/00qbcq685","country_code":"US","type":"company","lineage":["https://openalex.org/I4210095037"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Isam Akkawi","raw_affiliation_strings":["Cavium Networks, Marlborough, MA","Cavium Networks, 2315 N. First Street, San Jose, CA 95131, USA"],"affiliations":[{"raw_affiliation_string":"Cavium Networks, Marlborough, MA","institution_ids":["https://openalex.org/I4210095037"]},{"raw_affiliation_string":"Cavium Networks, 2315 N. First Street, San Jose, CA 95131, USA","institution_ids":["https://openalex.org/I4210095037"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014697202","display_name":"Jack Perveiler","orcid":null},"institutions":[{"id":"https://openalex.org/I4210095037","display_name":"Cavium (United States)","ror":"https://ror.org/00qbcq685","country_code":"US","type":"company","lineage":["https://openalex.org/I4210095037"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jack Perveiler","raw_affiliation_strings":["Cavium Networks, Marlborough, MA","Cavium Networks, 600 Nickerson Road, Marlborough, MA 01751, USA"],"affiliations":[{"raw_affiliation_string":"Cavium Networks, Marlborough, MA","institution_ids":["https://openalex.org/I4210095037"]},{"raw_affiliation_string":"Cavium Networks, 600 Nickerson Road, Marlborough, MA 01751, USA","institution_ids":["https://openalex.org/I4210095037"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102078684","display_name":"Jim Ellis","orcid":null},"institutions":[{"id":"https://openalex.org/I4210095037","display_name":"Cavium (United States)","ror":"https://ror.org/00qbcq685","country_code":"US","type":"company","lineage":["https://openalex.org/I4210095037"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jim Ellis","raw_affiliation_strings":["Cavium Networks, Marlborough, MA","Cavium Networks, 600 Nickerson Road, Marlborough, MA 01751, USA"],"affiliations":[{"raw_affiliation_string":"Cavium Networks, Marlborough, MA","institution_ids":["https://openalex.org/I4210095037"]},{"raw_affiliation_string":"Cavium Networks, 600 Nickerson Road, Marlborough, MA 01751, USA","institution_ids":["https://openalex.org/I4210095037"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5014045053"],"corresponding_institution_ids":["https://openalex.org/I4210095037"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.1042221,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"268","last_page":"273"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7632336020469666},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.67989182472229},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.6443979740142822},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.6221638917922974},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5694437623023987},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.5061683058738708},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.4843693673610687},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4557870924472809},{"id":"https://openalex.org/keywords/functional-verification","display_name":"Functional verification","score":0.44526100158691406},{"id":"https://openalex.org/keywords/time-to-market","display_name":"Time to market","score":0.44091707468032837},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4274991750717163},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.3507464528083801},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.19122958183288574}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7632336020469666},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.67989182472229},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.6443979740142822},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.6221638917922974},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5694437623023987},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.5061683058738708},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.4843693673610687},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4557870924472809},{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.44526100158691406},{"id":"https://openalex.org/C2779229675","wikidata":"https://www.wikidata.org/wiki/Q445235","display_name":"Time to market","level":2,"score":0.44091707468032837},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4274991750717163},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.3507464528083801},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.19122958183288574}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/socc.2014.6948939","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2014.6948939","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 27th IEEE International System-on-Chip Conference (SOCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.5099999904632568}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W68069235","https://openalex.org/W1943502734","https://openalex.org/W2095703264","https://openalex.org/W2097600002","https://openalex.org/W2098176818","https://openalex.org/W2114658430","https://openalex.org/W4251440867","https://openalex.org/W4252251132"],"related_works":["https://openalex.org/W75359960","https://openalex.org/W2105593427","https://openalex.org/W3120172095","https://openalex.org/W2118572231","https://openalex.org/W2059530328","https://openalex.org/W2116002481","https://openalex.org/W2259176885","https://openalex.org/W1585773602","https://openalex.org/W1498721867","https://openalex.org/W1583557603"],"abstract_inverted_index":{"We":[0],"are":[1],"presenting":[2],"a":[3,46,54],"hybrid":[4],"verification":[5],"framework":[6,15,77],"to":[7,71,80],"design,":[8],"verify":[9],"and":[10,40,89],"implement":[11],"SOC":[12,86],"protocols.":[13],"The":[14,49],"is":[16],"based":[17],"on":[18],"the":[19,37,58,69,74,81,90],"creation":[20,30],"of":[21,25,31,36,42,57,73,84],"specifications":[22],"in":[23,45,66],"terms":[24],"extended":[26],"state":[27],"transition":[28],"tables,":[29],"templates":[32],"for":[33],"different":[34,62],"phases":[35],"design":[38,47,51,63,82],"cycle":[39],"integration":[41,56],"these":[43],"components":[44],"flow.":[48],"resultant":[50],"flow":[52],"presents":[53],"tight":[55],"debug/verification":[59],"loop":[60],"across":[61],"stages":[64],"that":[65],"turn":[67],"reduce":[68],"time":[70],"market":[72],"chip.":[75],"This":[76],"was":[78],"applied":[79],"process":[83],"multiple":[85],"chips'":[87],"production":[88],"results":[91],"have":[92],"shown":[93],"measurable":[94],"enhancements.":[95]},"counts_by_year":[{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
