{"id":"https://openalex.org/W2089304204","doi":"https://doi.org/10.1109/socc.2014.6948913","title":"Design and implementation of novel source synchronous interconnection in modern GPU chips","display_name":"Design and implementation of novel source synchronous interconnection in modern GPU chips","publication_year":2014,"publication_date":"2014-09-01","ids":{"openalex":"https://openalex.org/W2089304204","doi":"https://doi.org/10.1109/socc.2014.6948913","mag":"2089304204"},"language":"en","primary_location":{"id":"doi:10.1109/socc.2014.6948913","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2014.6948913","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 27th IEEE International System-on-Chip Conference (SOCC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100455316","display_name":"Tao Li","orcid":"https://orcid.org/0000-0002-5333-0586"},"institutions":[{"id":"https://openalex.org/I1311921367","display_name":"Advanced Micro Devices (Canada)","ror":"https://ror.org/02yh0k313","country_code":"CA","type":"company","lineage":["https://openalex.org/I1311921367","https://openalex.org/I4210137977"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Tao Li","raw_affiliation_strings":["GPU group Advanced Macro Device (AMD), Shanghai, China","GPU group, Advanced Macro Device (AMD), Shanghai, China"],"affiliations":[{"raw_affiliation_string":"GPU group Advanced Macro Device (AMD), Shanghai, China","institution_ids":[]},{"raw_affiliation_string":"GPU group, Advanced Macro Device (AMD), Shanghai, China","institution_ids":["https://openalex.org/I1311921367"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040210678","display_name":"Greg Sadowski","orcid":null},"institutions":[{"id":"https://openalex.org/I1311921367","display_name":"Advanced Micro Devices (Canada)","ror":"https://ror.org/02yh0k313","country_code":"CA","type":"company","lineage":["https://openalex.org/I1311921367","https://openalex.org/I4210137977"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Greg Sadowski","raw_affiliation_strings":["Research Group Advanced Macro Device (AMD), Boxborough, US","Research Group, Advanced Macro Device (AMD), Boxborough, US"],"affiliations":[{"raw_affiliation_string":"Research Group Advanced Macro Device (AMD), Boxborough, US","institution_ids":[]},{"raw_affiliation_string":"Research Group, Advanced Macro Device (AMD), Boxborough, US","institution_ids":["https://openalex.org/I1311921367"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5100455316"],"corresponding_institution_ids":["https://openalex.org/I1311921367"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.16379759,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":93},"biblio":{"volume":null,"issue":null,"first_page":"130","last_page":"135"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7919084429740906},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.5345299243927002},{"id":"https://openalex.org/keywords/data-transmission","display_name":"Data transmission","score":0.48790499567985535},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.4413910508155823},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.41778916120529175},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.38904932141304016},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3585030734539032},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.11757314205169678}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7919084429740906},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.5345299243927002},{"id":"https://openalex.org/C557945733","wikidata":"https://www.wikidata.org/wiki/Q389772","display_name":"Data transmission","level":2,"score":0.48790499567985535},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.4413910508155823},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.41778916120529175},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.38904932141304016},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3585030734539032},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.11757314205169678},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/socc.2014.6948913","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2014.6948913","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 27th IEEE International System-on-Chip Conference (SOCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8600000143051147,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1517828062","https://openalex.org/W2122601433","https://openalex.org/W2125090069","https://openalex.org/W2141973190","https://openalex.org/W2148179047","https://openalex.org/W2156838846","https://openalex.org/W2410292773","https://openalex.org/W6678424324","https://openalex.org/W6714399718"],"related_works":["https://openalex.org/W2155019192","https://openalex.org/W2014709025","https://openalex.org/W2018755015","https://openalex.org/W1967979316","https://openalex.org/W2362533971","https://openalex.org/W2385795533","https://openalex.org/W2388210573","https://openalex.org/W2347964650","https://openalex.org/W2362169398","https://openalex.org/W2139353707"],"abstract_inverted_index":{"As":[0],"the":[1,53,72,81,90,108,127,173,177,192,198,202],"architecture":[2],"of":[3,16,52,74,114,176],"GPU":[4,65,123,161],"chips":[5],"evolves":[6],"to":[7,21,41,69,148,171,191],"provide":[8,149],"higher":[9,141],"performance":[10],"with":[11,71,133],"lower":[12],"power,":[13],"new":[14],"topology":[15],"graphics":[17],"shader":[18,45,146],"engines":[19,46],"interconnection":[20,29],"local":[22],"frame":[23,48],"buffers":[24,49],"becomes":[25],"critical.":[26],"Source":[27],"synchronous":[28,57,76,118,129],"has":[30],"been":[31],"widely":[32],"adopted":[33],"in":[34,67,80],"Network-On-Chip":[35],"(NoC).":[36],"The":[37],"SSB":[38,203],"bus":[39,130],"fabric":[40,159],"transfer":[42],"data":[43,101,157,179],"between":[44],"and":[47,93,111,139,185],"adopts":[50],"more":[51],"globally":[54],"asynchronous":[55],"locally":[56],"(GALS)":[58],"design":[59,109],"style":[60],"for":[61,121,160],"a":[62,115],"large":[63],"size":[64],"chip,":[66],"order":[68],"deal":[70],"challenge":[73],"delivering":[75],"high":[77,150,152],"frequencies":[78],"clocks":[79],"GHz":[82],"range":[83],"across":[84],"full":[85],"chip.":[86],"It":[87],"also":[88,164],"reduces":[89],"area":[91,155],"cost":[92,156],"power":[94,200],"consumption":[95],"on":[96,201],"long":[97],"distance":[98],"wide":[99],"width":[100],"transfer.":[102],"In":[103],"this":[104],"paper,":[105],"we":[106,194],"present":[107],"structure":[110,138],"physical":[112],"implementation":[113],"novel":[116],"source":[117,128],"interconnect":[119],"network":[120],"GALS-style":[122],"topology.":[124],"This":[125],"combines":[126],"lane":[131],"together":[132],"Multiple":[134],"Data":[135],"Rate":[136],"(MDR)":[137],"much":[140],"transmission":[142,158,204],"clock":[143,147,182],"frequency":[144],"than":[145],"bandwidth,":[151],"speed,":[153],"low":[154],"chips.":[162],"We":[163],"developed":[165],"MDR":[166,178,186],"signal":[167,187],"bits":[168],"encoding":[169,188],"techniques":[170,189],"reduce":[172,197],"toggle":[174],"rate":[175],"nets.":[180],"With":[181],"gating":[183],"scheme":[184],"adapted":[190],"applications,":[193],"could":[195],"further":[196],"total":[199],"fabric.":[205]},"counts_by_year":[{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}