{"id":"https://openalex.org/W1997379386","doi":"https://doi.org/10.1109/socc.2014.6948899","title":"A novel ratioed logic style for faster subthreshold digital circuits based on 90 nm CMOS and below","display_name":"A novel ratioed logic style for faster subthreshold digital circuits based on 90 nm CMOS and below","publication_year":2014,"publication_date":"2014-09-01","ids":{"openalex":"https://openalex.org/W1997379386","doi":"https://doi.org/10.1109/socc.2014.6948899","mag":"1997379386"},"language":"en","primary_location":{"id":"doi:10.1109/socc.2014.6948899","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2014.6948899","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 27th IEEE International System-on-Chip Conference (SOCC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101860041","display_name":"Weiwei Shi","orcid":"https://orcid.org/0000-0003-4551-8420"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"CN","type":"education","lineage":["https://openalex.org/I177725633"]},{"id":"https://openalex.org/I180726961","display_name":"Shenzhen University","ror":"https://ror.org/01vy4gh70","country_code":"CN","type":"education","lineage":["https://openalex.org/I180726961"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Weiwei Shi","raw_affiliation_strings":["College of Information Eng., Shenzhen University & Shenzhen Key Lab. of Advanced Communication and Information Processing","Department of Electronic Engineering, Chinese University of Hong Kong"],"affiliations":[{"raw_affiliation_string":"College of Information Eng., Shenzhen University & Shenzhen Key Lab. of Advanced Communication and Information Processing","institution_ids":["https://openalex.org/I180726961"]},{"raw_affiliation_string":"Department of Electronic Engineering, Chinese University of Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5020902784","display_name":"Chiu\u2010Sing Choy","orcid":"https://orcid.org/0000-0002-8370-3144"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"CN","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chiu-Sing Choy","raw_affiliation_strings":["Department of Electronic Engineering, Chinese University of Hong Kong"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Chinese University of Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5101860041"],"corresponding_institution_ids":["https://openalex.org/I177725633","https://openalex.org/I180726961"],"apc_list":null,"apc_paid":null,"fwci":0.1868,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.53832598,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"54","last_page":"57"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/subthreshold-conduction","display_name":"Subthreshold conduction","score":0.7392415404319763},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6853712201118469},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.6810244917869568},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.662731409072876},{"id":"https://openalex.org/keywords/pull-up-resistor","display_name":"Pull-up resistor","score":0.6345707178115845},{"id":"https://openalex.org/keywords/logic-level","display_name":"Logic level","score":0.6343665719032288},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5709621906280518},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.5691425800323486},{"id":"https://openalex.org/keywords/control-logic","display_name":"Control logic","score":0.5244072675704956},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5088379979133606},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4251979887485504},{"id":"https://openalex.org/keywords/integrated-injection-logic","display_name":"Integrated injection logic","score":0.4149664640426636},{"id":"https://openalex.org/keywords/and-or-invert","display_name":"AND-OR-Invert","score":0.4144444763660431},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.39406818151474},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.376108318567276},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.3584309220314026},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.289935827255249},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25738760828971863},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.2478533685207367},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.14270365238189697}],"concepts":[{"id":"https://openalex.org/C156465305","wikidata":"https://www.wikidata.org/wiki/Q1658601","display_name":"Subthreshold conduction","level":4,"score":0.7392415404319763},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6853712201118469},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.6810244917869568},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.662731409072876},{"id":"https://openalex.org/C61818909","wikidata":"https://www.wikidata.org/wiki/Q1987617","display_name":"Pull-up resistor","level":5,"score":0.6345707178115845},{"id":"https://openalex.org/C146569638","wikidata":"https://www.wikidata.org/wiki/Q173378","display_name":"Logic level","level":3,"score":0.6343665719032288},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5709621906280518},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.5691425800323486},{"id":"https://openalex.org/C2776350369","wikidata":"https://www.wikidata.org/wiki/Q843479","display_name":"Control logic","level":2,"score":0.5244072675704956},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5088379979133606},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4251979887485504},{"id":"https://openalex.org/C159903706","wikidata":"https://www.wikidata.org/wiki/Q173574","display_name":"Integrated injection logic","level":5,"score":0.4149664640426636},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.4144444763660431},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.39406818151474},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.376108318567276},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3584309220314026},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.289935827255249},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25738760828971863},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.2478533685207367},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.14270365238189697}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/socc.2014.6948899","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2014.6948899","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 27th IEEE International System-on-Chip Conference (SOCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.75}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1518236483","https://openalex.org/W2099144852","https://openalex.org/W2130948230","https://openalex.org/W2138111552","https://openalex.org/W2159448561","https://openalex.org/W6631122486"],"related_works":["https://openalex.org/W2171566066","https://openalex.org/W2114346412","https://openalex.org/W2580743037","https://openalex.org/W2178512053","https://openalex.org/W1900707063","https://openalex.org/W2622086348","https://openalex.org/W1995177342","https://openalex.org/W2539423522","https://openalex.org/W2291831650","https://openalex.org/W2182809268"],"abstract_inverted_index":{"An":[0],"innovative":[1],"logic":[2,9,30,75,79,112],"style":[3],"is":[4,21],"proposed":[5],"to":[6,40,68,115],"achieve":[7],"faster":[8,97],"propagation":[10],"in":[11,87],"subthreshold":[12],"operation:":[13],"the":[14,56,59,111],"Active":[15],"Controlled":[16],"Ratioed":[17],"Logic":[18],"(ACRL).":[19],"It":[20],"an":[22],"complete":[23],"improvement":[24],"and":[25,36,44,81,102,106],"optimization":[26],"from":[27],"previous":[28],"ratioed":[29],"styles":[31],"with":[32,107],"pull-up":[33],"current":[34,54],"control":[35,50],"modified":[37],"branches":[38],"tailored":[39],"very-low":[41],"supply":[42],"voltage":[43],"ultra-low":[45],"power.":[46],"Even":[47],"without":[48],"proper":[49],"of":[51,62,72,100],"its":[52],"load":[53],"at":[55],"pre-drive":[57],"stage,":[58],"active":[60],"power":[61,109],"ACRL":[63],"cells":[64,76,80],"can":[65],"be":[66],"suppressed":[67],"a":[69,116],"comparable":[70],"magnitude":[71],"static":[73,101],"CMOS":[74,90,104],"leakage.":[77],"General":[78],"complex":[82],"circuit":[83],"designs":[84],"were":[85],"fabricated":[86],"90":[88],"nm":[89],"technology.":[91],"In":[92],"measurement":[93],"they":[94],"are":[95],"30-70%":[96],"than":[98],"those":[99],"dynamic":[103],"styles,":[105],"lower":[108],"when":[110],"activity":[113],"rises":[114],"certain":[117],"level.":[118]},"counts_by_year":[{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
