{"id":"https://openalex.org/W2149353631","doi":"https://doi.org/10.1109/socc.2013.6749714","title":"A comprehensive operand-aware dynamic clock gating scheme for low-power Domino Logic","display_name":"A comprehensive operand-aware dynamic clock gating scheme for low-power Domino Logic","publication_year":2013,"publication_date":"2013-09-01","ids":{"openalex":"https://openalex.org/W2149353631","doi":"https://doi.org/10.1109/socc.2013.6749714","mag":"2149353631"},"language":"en","primary_location":{"id":"doi:10.1109/socc.2013.6749714","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2013.6749714","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE International SOC Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5082275270","display_name":"Salim Farah","orcid":null},"institutions":[{"id":"https://openalex.org/I79516672","display_name":"University of Louisiana at Lafayette","ror":"https://ror.org/01x8rc503","country_code":"US","type":"education","lineage":["https://openalex.org/I2799628689","https://openalex.org/I79516672"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Salim Farah","raw_affiliation_strings":["University of Louisiana at Lafayette, Louisiana, United States"],"affiliations":[{"raw_affiliation_string":"University of Louisiana at Lafayette, Louisiana, United States","institution_ids":["https://openalex.org/I79516672"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5010023744","display_name":"Magdy Bayoumi","orcid":"https://orcid.org/0000-0002-0630-5273"},"institutions":[{"id":"https://openalex.org/I79516672","display_name":"University of Louisiana at Lafayette","ror":"https://ror.org/01x8rc503","country_code":"US","type":"education","lineage":["https://openalex.org/I2799628689","https://openalex.org/I79516672"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Magdy Bayoumi","raw_affiliation_strings":["University of Louisiana at Lafayette, Louisiana, United States"],"affiliations":[{"raw_affiliation_string":"University of Louisiana at Lafayette, Louisiana, United States","institution_ids":["https://openalex.org/I79516672"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5082275270"],"corresponding_institution_ids":["https://openalex.org/I79516672"],"apc_list":null,"apc_paid":null,"fwci":0.2364,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.63320728,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"1","issue":null,"first_page":"349","last_page":"354"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/domino-logic","display_name":"Domino logic","score":0.8183158040046692},{"id":"https://openalex.org/keywords/operand","display_name":"Operand","score":0.7935807704925537},{"id":"https://openalex.org/keywords/domino","display_name":"Domino","score":0.7445117831230164},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.7089435458183289},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6554654836654663},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.6373875141143799},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.5651114583015442},{"id":"https://openalex.org/keywords/dynamic-demand","display_name":"Dynamic demand","score":0.5591099858283997},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.49282029271125793},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4456581771373749},{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.4242869019508362},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.41492176055908203},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.3671156167984009},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.31101781129837036},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.24629956483840942},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.2414979338645935},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.2299363613128662},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1915123164653778},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.16308480501174927},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.15575706958770752},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.14679235219955444},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.12299728393554688},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09199178218841553}],"concepts":[{"id":"https://openalex.org/C2777555262","wikidata":"https://www.wikidata.org/wiki/Q173391","display_name":"Domino logic","level":5,"score":0.8183158040046692},{"id":"https://openalex.org/C55526617","wikidata":"https://www.wikidata.org/wiki/Q719375","display_name":"Operand","level":2,"score":0.7935807704925537},{"id":"https://openalex.org/C2776416436","wikidata":"https://www.wikidata.org/wiki/Q3751781","display_name":"Domino","level":3,"score":0.7445117831230164},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.7089435458183289},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6554654836654663},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.6373875141143799},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.5651114583015442},{"id":"https://openalex.org/C45872418","wikidata":"https://www.wikidata.org/wiki/Q5318966","display_name":"Dynamic demand","level":3,"score":0.5591099858283997},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.49282029271125793},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4456581771373749},{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.4242869019508362},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.41492176055908203},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3671156167984009},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.31101781129837036},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.24629956483840942},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.2414979338645935},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2299363613128662},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1915123164653778},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.16308480501174927},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.15575706958770752},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.14679235219955444},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.12299728393554688},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09199178218841553},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C161790260","wikidata":"https://www.wikidata.org/wiki/Q82264","display_name":"Catalysis","level":2,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/socc.2013.6749714","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2013.6749714","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE International SOC Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8299999833106995,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1985055077","https://openalex.org/W2078992878","https://openalex.org/W2088675848","https://openalex.org/W2096382718","https://openalex.org/W2096663360","https://openalex.org/W2103880242","https://openalex.org/W2114020094","https://openalex.org/W2118216565","https://openalex.org/W2127195430","https://openalex.org/W2155611115","https://openalex.org/W2159868837","https://openalex.org/W2168226525","https://openalex.org/W4255639176"],"related_works":["https://openalex.org/W2152979262","https://openalex.org/W2485892467","https://openalex.org/W3127845477","https://openalex.org/W4252084893","https://openalex.org/W1949070338","https://openalex.org/W4390197045","https://openalex.org/W1510566755","https://openalex.org/W4562818","https://openalex.org/W2421981162","https://openalex.org/W2149353631"],"abstract_inverted_index":{"Domino":[0,20],"Logic's":[1],"excessive":[2],"power":[3,12,46],"consumption":[4],"limits":[5],"its":[6],"use":[7],"to":[8],"ICs":[9],"with":[10],"lax":[11],"budgets.":[13],"A":[14],"dynamic":[15],"clock":[16],"gating":[17],"scheme":[18],"for":[19],"that":[21],"takes":[22],"advantage":[23],"of":[24,27,59],"inactive":[25],"portions":[26],"functional":[28],"unit":[29],"operands":[30],"is":[31,48],"proposed.":[32],"Through":[33],"efficient":[34],"switching":[35],"activity":[36],"detection,":[37],"activity-domain":[38],"partitioning,":[39],"and":[40],"a":[41,51],"specific":[42],"multi-phase":[43],"configuration,":[44],"significant":[45],"saving":[47],"achieved":[49],"in":[50,63],"32-bit":[52],"Kogge":[53],"Stone":[54],"Adder":[55],"at":[56],"the":[57,64],"cost":[58],"increased":[60],"setup":[61],"time":[62],"preceding":[65],"pipeline":[66],"stage.":[67]},"counts_by_year":[{"year":2019,"cited_by_count":2},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
