{"id":"https://openalex.org/W2057608304","doi":"https://doi.org/10.1109/socc.2013.6749701","title":"Sleep transistor design in 28nm CMOS technology","display_name":"Sleep transistor design in 28nm CMOS technology","publication_year":2013,"publication_date":"2013-09-01","ids":{"openalex":"https://openalex.org/W2057608304","doi":"https://doi.org/10.1109/socc.2013.6749701","mag":"2057608304"},"language":"en","primary_location":{"id":"doi:10.1109/socc.2013.6749701","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2013.6749701","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE International SOC Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109555920","display_name":"Kaijian Shi","orcid":null},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Kaijian Shi","raw_affiliation_strings":["Cadence Design Systems, Dallas, USA","Cadence Design Syst., Dallas, TX, USA"],"affiliations":[{"raw_affiliation_string":"Cadence Design Systems, Dallas, USA","institution_ids":["https://openalex.org/I66217453"]},{"raw_affiliation_string":"Cadence Design Syst., Dallas, TX, USA","institution_ids":["https://openalex.org/I66217453"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5109555920"],"corresponding_institution_ids":["https://openalex.org/I66217453"],"apc_list":null,"apc_paid":null,"fwci":0.20656357,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.61434084,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"278","last_page":"283"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.8068752288818359},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7873350381851196},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4736177623271942},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.47209304571151733},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4695470929145813},{"id":"https://openalex.org/keywords/sleep","display_name":"Sleep (system call)","score":0.45751920342445374},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4542664587497711},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4357345700263977},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.30407336354255676},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.10285389423370361},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.062404900789260864}],"concepts":[{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.8068752288818359},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7873350381851196},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4736177623271942},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.47209304571151733},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4695470929145813},{"id":"https://openalex.org/C2775841894","wikidata":"https://www.wikidata.org/wiki/Q4683692","display_name":"Sleep (system call)","level":2,"score":0.45751920342445374},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4542664587497711},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4357345700263977},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.30407336354255676},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.10285389423370361},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.062404900789260864},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/socc.2013.6749701","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2013.6749701","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE International SOC Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.699999988079071}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W2022411221","https://openalex.org/W2027006313","https://openalex.org/W2109797003","https://openalex.org/W2124276471","https://openalex.org/W2125288742","https://openalex.org/W2126357937","https://openalex.org/W2131862714","https://openalex.org/W2146518537","https://openalex.org/W4235106764","https://openalex.org/W6681898109"],"related_works":["https://openalex.org/W3014521742","https://openalex.org/W2617868873","https://openalex.org/W3204141294","https://openalex.org/W4386230336","https://openalex.org/W4306968100","https://openalex.org/W2171986175","https://openalex.org/W2109445684","https://openalex.org/W2170979950","https://openalex.org/W1900707063","https://openalex.org/W2588941787"],"abstract_inverted_index":{"Significant":[0],"changes":[1],"in":[2,9],"transistor's":[3],"power-performance":[4],"characteristic":[5],"and":[6,32,35],"cross-corner":[7],"variations":[8],"28nm":[10],"CMOS":[11],"technology":[12],"prompt":[13],"the":[14],"need":[15],"for":[16,45],"a":[17],"new":[18],"look":[19],"at":[20],"sleep":[21,38],"transistor":[22,39],"design":[23,40,47],"guidelines.":[24],"This":[25],"paper":[26],"evaluated":[27],"impacts":[28],"of":[29],"back-bias,":[30],"Vt,":[31],"gate":[33],"length":[34],"width":[36],"on":[37],"quality.":[41],"Recommendations":[42],"were":[43],"proposed":[44],"production":[46],"considerations.":[48]},"counts_by_year":[{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
