{"id":"https://openalex.org/W2050265699","doi":"https://doi.org/10.1109/socc.2013.6749696","title":"Scalable system map library for address map and data integrity verification","display_name":"Scalable system map library for address map and data integrity verification","publication_year":2013,"publication_date":"2013-09-01","ids":{"openalex":"https://openalex.org/W2050265699","doi":"https://doi.org/10.1109/socc.2013.6749696","mag":"2050265699"},"language":"en","primary_location":{"id":"doi:10.1109/socc.2013.6749696","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2013.6749696","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE International SOC Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5112256903","display_name":"Prashanth Srinivasa","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Prashanth Srinivasa","raw_affiliation_strings":["Design Verification Engineer, LSI India R&D Pvt. Ltd., Bangalore, Karnataka, India","Design Verification Eng., LSI India R&D Pvt. Ltd., Bangalore, India"],"affiliations":[{"raw_affiliation_string":"Design Verification Engineer, LSI India R&D Pvt. Ltd., Bangalore, Karnataka, India","institution_ids":[]},{"raw_affiliation_string":"Design Verification Eng., LSI India R&D Pvt. Ltd., Bangalore, India","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5112256903"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.11373984,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"250","last_page":"255"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.802553117275238},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6728172302246094},{"id":"https://openalex.org/keywords/data-integrity","display_name":"Data integrity","score":0.577288031578064},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4997081756591797},{"id":"https://openalex.org/keywords/data-mapping","display_name":"Data mapping","score":0.42797261476516724},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.397123247385025},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3899083137512207},{"id":"https://openalex.org/keywords/database","display_name":"Database","score":0.36414581537246704}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.802553117275238},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6728172302246094},{"id":"https://openalex.org/C33762810","wikidata":"https://www.wikidata.org/wiki/Q461671","display_name":"Data integrity","level":2,"score":0.577288031578064},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4997081756591797},{"id":"https://openalex.org/C137314826","wikidata":"https://www.wikidata.org/wiki/Q2330408","display_name":"Data mapping","level":2,"score":0.42797261476516724},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.397123247385025},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3899083137512207},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.36414581537246704}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/socc.2013.6749696","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2013.6749696","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE International SOC Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":1,"referenced_works":["https://openalex.org/W1481733638"],"related_works":["https://openalex.org/W3142211975","https://openalex.org/W1879443270","https://openalex.org/W2018912978","https://openalex.org/W2130914040","https://openalex.org/W2119122672","https://openalex.org/W4292904049","https://openalex.org/W2136848245","https://openalex.org/W4213404769","https://openalex.org/W2118050502","https://openalex.org/W1485984927"],"abstract_inverted_index":{"Address":[0],"map":[1,33],"and":[2,19,34,41,70,91],"data":[3,35],"integrity":[4,36],"verification":[5,14,37],"are":[6],"the":[7,25,28,59,63,80,87],"most":[8],"important":[9],"parts":[10],"of":[11,31,38],"SoC":[12,40],"(System-on-Chip)":[13],"especially":[15],"at":[16],"interconnect,":[17],"sub-system":[18],"chip":[20],"level.":[21],"This":[22],"paper":[23,57],"discusses":[24],"challenges":[26,45],"in":[27,85],"traditional":[29],"way":[30],"address":[32],"today's":[39],"describes":[42],"how":[43,79],"these":[44],"were":[46,83],"addressed":[47],"by":[48,62],"a":[49,71],"SystemVerilog":[50],"based":[51],"Scalable":[52],"System":[53],"Map":[54],"library.":[55],"The":[56],"explains":[58,78],"facilities":[60],"provided":[61],"library":[64,88],"for":[65],"generating":[66],"random":[67],"stimulus,":[68],"scoreboarding":[69],"built-in":[72],"functional":[73],"coverage":[74],"model.":[75],"It":[76],"also":[77],"language":[81],"limitations":[82],"tackled":[84],"making":[86],"reusable":[89],"within":[90],"across":[92],"projects.":[93]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
