{"id":"https://openalex.org/W1979543547","doi":"https://doi.org/10.1109/socc.2013.6749676","title":"Tutorial: Methodology for designing reliable clock networks","display_name":"Tutorial: Methodology for designing reliable clock networks","publication_year":2013,"publication_date":"2013-09-01","ids":{"openalex":"https://openalex.org/W1979543547","doi":"https://doi.org/10.1109/socc.2013.6749676","mag":"1979543547"},"language":"en","primary_location":{"id":"doi:10.1109/socc.2013.6749676","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2013.6749676","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE International SOC Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101736516","display_name":"Taewhan Kim","orcid":"https://orcid.org/0000-0003-2376-4970"},"institutions":[{"id":"https://openalex.org/I139264467","display_name":"Seoul National University","ror":"https://ror.org/04h9pn542","country_code":"KR","type":"education","lineage":["https://openalex.org/I139264467"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"Taewhan Kim","raw_affiliation_strings":["Seoul National University, Gwanak-gu, Seoul, KR","Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ. Seoul, South Korea"],"affiliations":[{"raw_affiliation_string":"Seoul National University, Gwanak-gu, Seoul, KR","institution_ids":["https://openalex.org/I139264467"]},{"raw_affiliation_string":"Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ. Seoul, South Korea","institution_ids":["https://openalex.org/I139264467"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5101736516"],"corresponding_institution_ids":["https://openalex.org/I139264467"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.05523667,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"141","last_page":"141"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.7288108468055725},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.727156400680542},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.6611908674240112},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5791144967079163},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.552513062953949},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.46242302656173706},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.4463992714881897},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.42521408200263977},{"id":"https://openalex.org/keywords/variation","display_name":"Variation (astronomy)","score":0.42480623722076416},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.35520198941230774},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.34067732095718384},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.3025021553039551},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2769767642021179},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09897246956825256},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.085970938205719},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.08554190397262573}],"concepts":[{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.7288108468055725},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.727156400680542},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.6611908674240112},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5791144967079163},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.552513062953949},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.46242302656173706},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.4463992714881897},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.42521408200263977},{"id":"https://openalex.org/C2778334786","wikidata":"https://www.wikidata.org/wiki/Q1586270","display_name":"Variation (astronomy)","level":2,"score":0.42480623722076416},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.35520198941230774},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.34067732095718384},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.3025021553039551},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2769767642021179},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09897246956825256},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.085970938205719},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.08554190397262573},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C44870925","wikidata":"https://www.wikidata.org/wiki/Q37547","display_name":"Astrophysics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/socc.2013.6749676","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2013.6749676","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE International SOC Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5,"id":"https://metadata.un.org/sdg/11","display_name":"Sustainable cities and communities"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2087612346","https://openalex.org/W2075400577","https://openalex.org/W2144518356","https://openalex.org/W2128060653","https://openalex.org/W2121694082","https://openalex.org/W2164715378","https://openalex.org/W2114711633","https://openalex.org/W1989962531","https://openalex.org/W2124083463","https://openalex.org/W2135926377"],"abstract_inverted_index":{"This":[0],"tutorial":[1],"covers":[2],"the":[3,11,21,31,40,49,54,62,70,73,97,104,111],"clock":[4,15,26,77,98],"network":[5],"design":[6,41,64,99],"methodology,":[7],"especially":[8],"focusing":[9],"on":[10],"construction":[12],"of":[13,25,33,76,106],"robust":[14],"under":[16],"PVT":[17,55],"(process-voltage-temperature)":[18],"variation.":[19],"First,":[20],"basic":[22],"synthesis":[23],"flow":[24,100],"networks":[27,78],"is":[28,101],"described":[29],"with":[30,88],"emphasis":[32],"key":[34],"factors":[35],"to":[36,68,103,114],"be":[37,115,125],"considered":[38],"during":[39],"process.":[42],"Second,":[43],"a":[44,89],"more":[45],"in-depth":[46],"analysis":[47],"and":[48,65,81,84,109,118],"related":[50],"problems":[51],"caused":[52],"by":[53,60],"variation":[56],"are":[57,79,86,117,121],"discussed,":[58],"followed":[59],"enumerating":[61],"state-of-art":[63],"optimization":[66],"techniques":[67],"address":[69],"problems.":[71],"Thirdly,":[72],"diverse":[74],"structures":[75],"described,":[80],"their":[82],"pros":[83],"cons":[85],"summarized":[87],"numeric":[90],"data":[91],"extracted":[92],"from":[93],"intensive":[94],"simulation.":[95],"Finally,":[96],"moved":[102],"area":[105],"3D":[107],"ICs,":[108],"what":[110],"unique":[112],"issues":[113],"addressed":[116],"how":[119],"they":[120],"currently":[122],"solved":[123],"will":[124],"presented.":[126]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
