{"id":"https://openalex.org/W1980989199","doi":"https://doi.org/10.1109/socc.2013.6749669","title":"Method for resolving simultaneous same-row access in Dual-Port 8T SRAM with asynchronous dual-clock operation","display_name":"Method for resolving simultaneous same-row access in Dual-Port 8T SRAM with asynchronous dual-clock operation","publication_year":2013,"publication_date":"2013-09-01","ids":{"openalex":"https://openalex.org/W1980989199","doi":"https://doi.org/10.1109/socc.2013.6749669","mag":"1980989199"},"language":"en","primary_location":{"id":"doi:10.1109/socc.2013.6749669","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2013.6749669","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE International SOC Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111563409","display_name":"Nan-Chun Lien","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Nan-Chun Lien","raw_affiliation_strings":["Dept. of Electrical and Computer Engineering, National Chiao Tung University, Hsinchu, Taiwan, R.O.C","Dept. of Electron. Eng, Nat. Chiao Tung Univ, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Computer Engineering, National Chiao Tung University, Hsinchu, Taiwan, R.O.C","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Dept. of Electron. Eng, Nat. Chiao Tung Univ, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039359237","display_name":"Ching-Te Chuang","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ching-Te Chuang","raw_affiliation_strings":["Dept. of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan, R.O.C","Dept. of Electron. Eng, Nat. Chiao Tung Univ, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Dept. of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan, R.O.C","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Dept. of Electron. Eng, Nat. Chiao Tung Univ, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5084663385","display_name":"Wen-Rong Wu","orcid":"https://orcid.org/0000-0001-8333-7124"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Wen-Rong Wu","raw_affiliation_strings":["Dept. of Electrical and Computer Engineering, National Chiao Tung University, Hsinchu, Taiwan, R.O.C","[Dept. of Electr. & Comput. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan]"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Computer Engineering, National Chiao Tung University, Hsinchu, Taiwan, R.O.C","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"[Dept. of Electr. & Comput. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan]","institution_ids":["https://openalex.org/I148366613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5111563409"],"corresponding_institution_ids":["https://openalex.org/I148366613"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.05652829,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"105","last_page":"109"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.7580024003982544},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7269960641860962},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6664656400680542},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.6543287038803101},{"id":"https://openalex.org/keywords/dual","display_name":"Dual (grammatical number)","score":0.6111671328544617},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.5099016427993774},{"id":"https://openalex.org/keywords/port","display_name":"Port (circuit theory)","score":0.5078158974647522},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.4958733022212982},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.4667202830314636},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.43806034326553345},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.4149187505245209},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.39473289251327515},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.36659151315689087},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.35363680124282837},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.23999792337417603},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.1645367443561554},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.16296109557151794},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.1259118914604187},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12182614207267761},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09098568558692932},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07428443431854248}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.7580024003982544},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7269960641860962},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6664656400680542},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.6543287038803101},{"id":"https://openalex.org/C2780980858","wikidata":"https://www.wikidata.org/wiki/Q110022","display_name":"Dual (grammatical number)","level":2,"score":0.6111671328544617},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.5099016427993774},{"id":"https://openalex.org/C32802771","wikidata":"https://www.wikidata.org/wiki/Q2443617","display_name":"Port (circuit theory)","level":2,"score":0.5078158974647522},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.4958733022212982},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.4667202830314636},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.43806034326553345},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.4149187505245209},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.39473289251327515},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.36659151315689087},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.35363680124282837},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.23999792337417603},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.1645367443561554},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.16296109557151794},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.1259118914604187},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12182614207267761},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09098568558692932},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07428443431854248},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C124952713","wikidata":"https://www.wikidata.org/wiki/Q8242","display_name":"Literature","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/socc.2013.6749669","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2013.6749669","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE International SOC Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.6600000262260437}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1992606738","https://openalex.org/W2002612140","https://openalex.org/W2095953597","https://openalex.org/W2123278390","https://openalex.org/W2158933924","https://openalex.org/W2162335740","https://openalex.org/W2165720303","https://openalex.org/W4244763807"],"related_works":["https://openalex.org/W2164834710","https://openalex.org/W4232019485","https://openalex.org/W2028052815","https://openalex.org/W2076413498","https://openalex.org/W4327499872","https://openalex.org/W2123512677","https://openalex.org/W2116259070","https://openalex.org/W2128528443","https://openalex.org/W2066822161","https://openalex.org/W2097706495"],"abstract_inverted_index":{"This":[0],"work":[1],"proposes":[2],"a":[3],"novel":[4],"Dual-Port":[5],"(DP)":[6],"8T":[7],"SRAM":[8],"operation":[9,22],"scheme.":[10],"The":[11],"scheme":[12],"improves":[13],"the":[14,60,64],"Read":[15],"stability":[16],"and":[17,19,36,45,59],"Write-ability,":[18],"allows":[20],"asynchronous":[21],"with":[23,42],"arbitrary":[24],"clock":[25],"timing":[26,53],"skew":[27],"between":[28],"two":[29],"ports.":[30],"It":[31],"facilitates":[32],"high":[33],"performance,":[34],"low-power":[35],"low":[37],"V":[38],"<sub":[39],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[40],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">MIN</sub>":[41],"minimum":[43],"device":[44],"area":[46],"overhead.":[47],"Post-simulation":[48],"results":[49],"show":[50],"almost":[51,63],"no":[52],"penalty":[54],"for":[55,68],"simultaneous":[56],"same-row":[57],"access":[58],"performance":[61],"is":[62],"same":[65],"as":[66],"that":[67],"one":[69],"port":[70],"operation.":[71]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
