{"id":"https://openalex.org/W2085099261","doi":"https://doi.org/10.1109/socc.2013.6749656","title":"Design of 2&amp;#x00D7;V&lt;inf&gt;DD&lt;/inf&gt; logic gates with only 1&amp;#x00D7;V&lt;inf&gt;DD&lt;/inf&gt; devices in nanoscale CMOS technology","display_name":"Design of 2&amp;#x00D7;V&lt;inf&gt;DD&lt;/inf&gt; logic gates with only 1&amp;#x00D7;V&lt;inf&gt;DD&lt;/inf&gt; devices in nanoscale CMOS technology","publication_year":2013,"publication_date":"2013-09-01","ids":{"openalex":"https://openalex.org/W2085099261","doi":"https://doi.org/10.1109/socc.2013.6749656","mag":"2085099261"},"language":"en","primary_location":{"id":"doi:10.1109/socc.2013.6749656","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2013.6749656","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE International SOC Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108249057","display_name":"Po-Yen Chiu","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Po-Yen Chiu","raw_affiliation_strings":["Nanoelectronics and Gigascale Systems Laboratory Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan","Nanoelectron. & Gigascale Syst. Lab., Nat. Chiao-Tung Univ., Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Nanoelectronics and Gigascale Systems Laboratory Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Nanoelectron. & Gigascale Syst. Lab., Nat. Chiao-Tung Univ., Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043540734","display_name":"Ming\u2010Dou Ker","orcid":"https://orcid.org/0000-0003-3622-181X"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ming-Dou Ker","raw_affiliation_strings":["Nanoelectronics and Gigascale Systems Laboratory Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan","Nanoelectron. & Gigascale Syst. Lab., Nat. Chiao-Tung Univ., Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Nanoelectronics and Gigascale Systems Laboratory Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Nanoelectron. & Gigascale Syst. Lab., Nat. Chiao-Tung Univ., Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5108249057"],"corresponding_institution_ids":["https://openalex.org/I148366613"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.13641302,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"33","last_page":"36"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.6487367153167725},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5364281535148621},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5236306190490723},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4218197464942932},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.4136947989463806},{"id":"https://openalex.org/keywords/and-gate","display_name":"AND gate","score":0.4125382602214813},{"id":"https://openalex.org/keywords/nor-gate","display_name":"NOR gate","score":0.41048210859298706},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.410106897354126},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.39624154567718506},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.3677728474140167},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.3190998435020447},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16433554887771606},{"id":"https://openalex.org/keywords/quantum-mechanics","display_name":"Quantum mechanics","score":0.06872493028640747}],"concepts":[{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.6487367153167725},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5364281535148621},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5236306190490723},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4218197464942932},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.4136947989463806},{"id":"https://openalex.org/C10418432","wikidata":"https://www.wikidata.org/wiki/Q560370","display_name":"AND gate","level":3,"score":0.4125382602214813},{"id":"https://openalex.org/C126445297","wikidata":"https://www.wikidata.org/wiki/Q8065380","display_name":"NOR gate","level":4,"score":0.41048210859298706},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.410106897354126},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.39624154567718506},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3677728474140167},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.3190998435020447},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16433554887771606},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.06872493028640747},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/socc.2013.6749656","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2013.6749656","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE International SOC Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.44999998807907104,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W2098629800","https://openalex.org/W2102434753","https://openalex.org/W2126232622","https://openalex.org/W2140229217","https://openalex.org/W2161776378","https://openalex.org/W2197532981","https://openalex.org/W6675034984"],"related_works":["https://openalex.org/W2515312339","https://openalex.org/W1017999001","https://openalex.org/W2145098804","https://openalex.org/W2765195743","https://openalex.org/W2130440338","https://openalex.org/W2616524835","https://openalex.org/W2161229876","https://openalex.org/W2760870732","https://openalex.org/W2774826444","https://openalex.org/W2791832526"],"abstract_inverted_index":{"The":[0],"novel":[1],"2\u00d7V":[2,44,53,63],"<sub":[3,25,45,54,64],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[4,26,46,55,65],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">DD</sub>":[5,27,47,56,66],"NOT,":[6],"NAND,":[7],"and":[8,15],"NOR":[9],"logic":[10,37,57],"gates":[11,38,58],"have":[12,43],"been":[13],"designed":[14,41],"implemented":[16],"in":[17],"a":[18],"nanoscale":[19],"CMOS":[20],"process":[21],"with":[22],"only":[23],"1\u00d7V":[24],"devices.":[28],"With":[29],"the":[30,36,51,71],"proposed":[31],"dynamic":[32],"source":[33],"bias":[34],"technique,":[35],"can":[39,59],"be":[40,60],"to":[42],"tolerant":[48],"capability.":[49],"Thus,":[50],"new":[52],"operated":[61],"under":[62],"voltage":[67],"environment":[68],"without":[69],"suffering":[70],"gate-oxide":[72],"reliability":[73],"issue.":[74]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}