{"id":"https://openalex.org/W2092483197","doi":"https://doi.org/10.1109/socc.2012.6398384","title":"Reconfigurable RRAM for LUT logic mapping: A case study for reliability enhancement","display_name":"Reconfigurable RRAM for LUT logic mapping: A case study for reliability enhancement","publication_year":2012,"publication_date":"2012-09-01","ids":{"openalex":"https://openalex.org/W2092483197","doi":"https://doi.org/10.1109/socc.2012.6398384","mag":"2092483197"},"language":"en","primary_location":{"id":"doi:10.1109/socc.2012.6398384","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2012.6398384","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International SOC Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5001841804","display_name":"Matthew M. Catanzaro","orcid":null},"institutions":[{"id":"https://openalex.org/I155173764","display_name":"Rochester Institute of Technology","ror":"https://ror.org/00v4yb702","country_code":"US","type":"education","lineage":["https://openalex.org/I155173764"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Matthew Catanzaro","raw_affiliation_strings":["NanoComputing Research Group, Department of Computer Engineering, Rochester Institute of Technology, New York, USA","NanoComputing Research Group, Department of Computer Engineering, Rochester Institute of Technology, New York 14623"],"affiliations":[{"raw_affiliation_string":"NanoComputing Research Group, Department of Computer Engineering, Rochester Institute of Technology, New York, USA","institution_ids":["https://openalex.org/I155173764"]},{"raw_affiliation_string":"NanoComputing Research Group, Department of Computer Engineering, Rochester Institute of Technology, New York 14623","institution_ids":["https://openalex.org/I155173764"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5067236813","display_name":"Dhireesha Kudithipudi","orcid":"https://orcid.org/0000-0003-4462-5224"},"institutions":[{"id":"https://openalex.org/I155173764","display_name":"Rochester Institute of Technology","ror":"https://ror.org/00v4yb702","country_code":"US","type":"education","lineage":["https://openalex.org/I155173764"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dhireesha Kudithipudi","raw_affiliation_strings":["NanoComputing Research Group, Department of Computer Engineering, Rochester Institute of Technology, New York, USA","NanoComputing Research Group, Department of Computer Engineering, Rochester Institute of Technology, New York 14623"],"affiliations":[{"raw_affiliation_string":"NanoComputing Research Group, Department of Computer Engineering, Rochester Institute of Technology, New York, USA","institution_ids":["https://openalex.org/I155173764"]},{"raw_affiliation_string":"NanoComputing Research Group, Department of Computer Engineering, Rochester Institute of Technology, New York 14623","institution_ids":["https://openalex.org/I155173764"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5001841804"],"corresponding_institution_ids":["https://openalex.org/I155173764"],"apc_list":null,"apc_paid":null,"fwci":0.2455,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.61445837,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"94","last_page":"99"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.8545231819152832},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6325072050094604},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6275572180747986},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.599578320980072},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.557116687297821},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.5389266014099121},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.525700569152832},{"id":"https://openalex.org/keywords/soft-error","display_name":"Soft error","score":0.4876348078250885},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4767281115055084},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.472141295671463},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.45682600140571594},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.4538125693798065},{"id":"https://openalex.org/keywords/circuit-reliability","display_name":"Circuit reliability","score":0.45248252153396606},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.43024927377700806},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.42426568269729614},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.2586762309074402},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.22324374318122864},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20302879810333252},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.20067301392555237},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.19757777452468872},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.12895935773849487}],"concepts":[{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.8545231819152832},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6325072050094604},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6275572180747986},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.599578320980072},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.557116687297821},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.5389266014099121},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.525700569152832},{"id":"https://openalex.org/C154474529","wikidata":"https://www.wikidata.org/wiki/Q1658917","display_name":"Soft error","level":2,"score":0.4876348078250885},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4767281115055084},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.472141295671463},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.45682600140571594},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.4538125693798065},{"id":"https://openalex.org/C2778309119","wikidata":"https://www.wikidata.org/wiki/Q5121614","display_name":"Circuit reliability","level":4,"score":0.45248252153396606},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.43024927377700806},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.42426568269729614},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.2586762309074402},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.22324374318122864},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20302879810333252},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.20067301392555237},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.19757777452468872},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.12895935773849487},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/socc.2012.6398384","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2012.6398384","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International SOC Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8700000047683716,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":28,"referenced_works":["https://openalex.org/W1565771925","https://openalex.org/W1852762474","https://openalex.org/W1997611279","https://openalex.org/W2007750458","https://openalex.org/W2021216084","https://openalex.org/W2096286660","https://openalex.org/W2102255233","https://openalex.org/W2104086123","https://openalex.org/W2106863684","https://openalex.org/W2112181056","https://openalex.org/W2129857517","https://openalex.org/W2129955113","https://openalex.org/W2132490082","https://openalex.org/W2139203854","https://openalex.org/W2147657366","https://openalex.org/W2148331362","https://openalex.org/W2156299553","https://openalex.org/W2167607185","https://openalex.org/W2170382128","https://openalex.org/W2323986115","https://openalex.org/W2497735908","https://openalex.org/W2539432805","https://openalex.org/W2539856142","https://openalex.org/W2545789532","https://openalex.org/W2725179571","https://openalex.org/W3182208082","https://openalex.org/W4231523873","https://openalex.org/W6675347859"],"related_works":["https://openalex.org/W2090025763","https://openalex.org/W2535854306","https://openalex.org/W2043393912","https://openalex.org/W2460159704","https://openalex.org/W1996241861","https://openalex.org/W2166056129","https://openalex.org/W3141764359","https://openalex.org/W3179888111","https://openalex.org/W3048013713","https://openalex.org/W2170534122"],"abstract_inverted_index":{"Emerging":[0],"hybrid-CMOS":[1],"nanoscale":[2],"devices":[3],"and":[4,11,25,45,55,153],"architectures":[5,71],"offer":[6],"greater":[7],"degree":[8],"of":[9,122,146,151,156,161],"integration":[10],"performance":[12],"capabilities.":[13],"However,":[14],"the":[15,29,47,63,78,89,94,106,132],"high":[16,53],"power":[17,56],"densities,":[18],"hard":[19],"error/soft":[20],"error":[21],"frequency,":[22],"process":[23],"variations,":[24],"device":[26],"wearout":[27],"affect":[28],"overall":[30],"system":[31,48,64],"reliability.":[32],"Reactive":[33],"design":[34],"techniques,":[35],"such":[36],"as":[37,98],"redundancy,":[38],"account":[39],"for":[40,124],"component":[41],"failures":[42],"by":[43,72,92],"detecting":[44],"correcting":[46],"failures.":[49],"These":[50],"techniques":[51],"incur":[52],"area":[54],"overhead.":[57],"Our":[58,128],"research":[59],"focuses":[60],"on":[61,113],"enhancing":[62],"reliability":[65],"in":[66,75,105,142],"hybrid":[67],"CMOS/Resistive":[68],"RAM":[69],"(RRAM)":[70],"performing":[73],"computation":[74],"RRAM,":[76],"whenever":[77],"CMOS":[79,96],"logic":[80,103],"units":[81,97,139],"fail.":[82],"In":[83],"particular,":[84],"we":[85],"propose":[86],"dynamically":[87],"reconfiguring":[88],"RRAM":[90],"cache":[91,123],"mapping":[93],"failed":[95,138],"look":[99],"up":[100,147,157],"table":[101],"(LUT)":[102],"blocks":[104],"RRAM.":[107,143],"The":[108],"proposed":[109],"approach":[110],"is":[111,134,163],"validated":[112],"a":[114],"45nm":[115],"single":[116],"core":[117,133],"processor":[118],"with":[119],"three":[120],"levels":[121],"various":[125],"SPEC2006":[126],"benchmarks.":[127],"results":[129],"demonstrate":[130],"that":[131],"fully":[135],"functional":[136],"when":[137],"are":[140],"reconfigured":[141],"Performance":[144],"degradation":[145],"to":[148,158],"one":[149],"order":[150],"magnitude":[152,162],"energy":[154],"increase":[155],"two":[159],"orders":[160],"observed.":[164]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}