{"id":"https://openalex.org/W1992087818","doi":"https://doi.org/10.1109/socc.2012.6398365","title":"Exploiting memristive device behavior for emerging digital logic and memory applications","display_name":"Exploiting memristive device behavior for emerging digital logic and memory applications","publication_year":2012,"publication_date":"2012-09-01","ids":{"openalex":"https://openalex.org/W1992087818","doi":"https://doi.org/10.1109/socc.2012.6398365","mag":"1992087818"},"language":"en","primary_location":{"id":"doi:10.1109/socc.2012.6398365","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2012.6398365","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International SOC Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5040556213","display_name":"Garret S. Rose","orcid":null},"institutions":[{"id":"https://openalex.org/I1280414376","display_name":"United States Air Force Research Laboratory","ror":"https://ror.org/02e2egq70","country_code":"US","type":"facility","lineage":["https://openalex.org/I1280414376","https://openalex.org/I1330347796","https://openalex.org/I4210102105","https://openalex.org/I4389425425"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Garret S. Rose","raw_affiliation_strings":["Information Directorate, Air Force Research Laboratory, Rome, NY, USA","Information Directorate, Air Force Research Laboratory , Rome, NY, USA"],"affiliations":[{"raw_affiliation_string":"Information Directorate, Air Force Research Laboratory, Rome, NY, USA","institution_ids":["https://openalex.org/I1280414376"]},{"raw_affiliation_string":"Information Directorate, Air Force Research Laboratory , Rome, NY, USA","institution_ids":["https://openalex.org/I1280414376"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5040556213"],"corresponding_institution_ids":["https://openalex.org/I1280414376"],"apc_list":null,"apc_paid":null,"fwci":0.2455,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.57160024,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"292","last_page":"292"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.8760204315185547},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6654806137084961},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5554788112640381},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5505853891372681},{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.5494928359985352},{"id":"https://openalex.org/keywords/forcing","display_name":"Forcing (mathematics)","score":0.5494623780250549},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.5373721122741699},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5151699781417847},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5140410661697388},{"id":"https://openalex.org/keywords/resistor","display_name":"Resistor","score":0.4760977029800415},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.46675682067871094},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.345057874917984},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.226654052734375},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.1159810721874237}],"concepts":[{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.8760204315185547},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6654806137084961},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5554788112640381},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5505853891372681},{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.5494928359985352},{"id":"https://openalex.org/C197115733","wikidata":"https://www.wikidata.org/wiki/Q1003136","display_name":"Forcing (mathematics)","level":2,"score":0.5494623780250549},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.5373721122741699},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5151699781417847},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5140410661697388},{"id":"https://openalex.org/C137488568","wikidata":"https://www.wikidata.org/wiki/Q5321","display_name":"Resistor","level":3,"score":0.4760977029800415},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.46675682067871094},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.345057874917984},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.226654052734375},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.1159810721874237},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.0},{"id":"https://openalex.org/C49204034","wikidata":"https://www.wikidata.org/wiki/Q52139","display_name":"Climatology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/socc.2012.6398365","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2012.6398365","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International SOC Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W3173413269","https://openalex.org/W1980349267","https://openalex.org/W2098419840","https://openalex.org/W2140610743","https://openalex.org/W2116326546","https://openalex.org/W2097637358","https://openalex.org/W2151104031","https://openalex.org/W2765435638","https://openalex.org/W3134372534","https://openalex.org/W2121863912"],"abstract_inverted_index":{"In":[0,92],"many":[1,36],"ways,":[2],"conventional":[3,33,90],"integrated":[4],"circuit":[5,51],"technology":[6,114],"(i.e.,":[7],"bulk":[8],"Si":[9],"CMOS)":[10],"continues":[11,35],"to":[12,55,67,78,135,151],"follow":[13],"the":[14,26,30,69,120,157],"predictions":[15],"of":[16,32,72,115,129,159,170,175,187],"Moore's":[17],"Law":[18],"but":[19,104],"true":[20],"physical":[21],"limits":[22],"are":[23,49],"lurking":[24],"around":[25],"corner.":[27],"Even":[28],"as":[29],"scaling":[31],"technologies":[34,155],"performance":[37,102],"issues":[38],"(e.g.,":[39,76],"high":[40],"power":[41],"dissipation,":[42],"increasing":[43],"thermal":[44],"effects,":[45],"and":[46,52,142,166,177,197],"process":[47],"variations)":[48],"forcing":[50],"microarchitectural":[53],"designers":[54],"look":[56],"for":[57,60,110,117,139],"novel":[58,73,80],"approaches":[59],"emerging":[61,95,140],"systems.":[62,143,167],"One":[63],"such":[64],"direction":[65],"is":[66],"utilize":[68],"unconventional":[70],"behavior":[71],"nanoelectronic":[74],"devices":[75,162,190],"memristors)":[77],"develop":[79,152],"computational":[81],"architectures":[82,96],"that":[83],"may":[84,97,105],"not":[85,98],"be":[86,181,192],"reasonably":[87],"implementable":[88],"using":[89],"CMOS.":[91],"this":[93,118,171],"way,":[94],"only":[99],"allow":[100],"continued":[101],"improvements":[103],"also":[106],"open":[107],"new":[108],"avenues":[109],"computing.":[111],"The":[112],"particular":[113],"interest":[116,130],"talk,":[119,172],"memristor":[121],"or":[122],"memory":[123,198],"resistor,":[124],"has":[125],"gained":[126],"a":[127],"lot":[128],"in":[131,194],"recent":[132],"years":[133],"due":[134],"its":[136],"great":[137],"potential":[138],"circuits":[141,165],"We":[144],"have":[145],"been":[146],"working":[147],"with":[148,156,184],"several":[149],"collaborators":[150],"memristive":[153,178],"device":[154],"goal":[158],"integrating":[160],"these":[161,189],"into":[163],"digital":[164,195],"As":[168],"part":[169],"an":[173],"overview":[174],"memristors":[176],"systems":[179],"will":[180],"provided":[182],"along":[183],"some":[185],"exploration":[186],"how":[188],"can":[191],"leveraged":[193],"logic":[196],"circuits.":[199]},"counts_by_year":[{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}