{"id":"https://openalex.org/W1971611738","doi":"https://doi.org/10.1109/socc.2012.6398359","title":"Multi-Clock DFT architecture for interface characterization and power","display_name":"Multi-Clock DFT architecture for interface characterization and power","publication_year":2012,"publication_date":"2012-09-01","ids":{"openalex":"https://openalex.org/W1971611738","doi":"https://doi.org/10.1109/socc.2012.6398359","mag":"1971611738"},"language":"en","primary_location":{"id":"doi:10.1109/socc.2012.6398359","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2012.6398359","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International SOC Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5047074275","display_name":"C.A. Ryan","orcid":null},"institutions":[{"id":"https://openalex.org/I47646028","display_name":"Maxim Integrated (United Kingdom)","ror":"https://ror.org/004b7jc50","country_code":"GB","type":"company","lineage":["https://openalex.org/I4210152613","https://openalex.org/I47646028"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Christopher Ryan","raw_affiliation_strings":["Maxim Integrated Products, India","Maxim Integrated"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Maxim Integrated Products, India","institution_ids":[]},{"raw_affiliation_string":"Maxim Integrated","institution_ids":["https://openalex.org/I47646028"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086127027","display_name":"Kris Monsen","orcid":null},"institutions":[{"id":"https://openalex.org/I47646028","display_name":"Maxim Integrated (United Kingdom)","ror":"https://ror.org/004b7jc50","country_code":"GB","type":"company","lineage":["https://openalex.org/I4210152613","https://openalex.org/I47646028"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Kris Monsen","raw_affiliation_strings":["Maxim Integrated Products, India","Maxim Integrated"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Maxim Integrated Products, India","institution_ids":[]},{"raw_affiliation_string":"Maxim Integrated","institution_ids":["https://openalex.org/I47646028"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037749034","display_name":"Scott C. Smith","orcid":"https://orcid.org/0000-0001-9863-6637"},"institutions":[{"id":"https://openalex.org/I47646028","display_name":"Maxim Integrated (United Kingdom)","ror":"https://ror.org/004b7jc50","country_code":"GB","type":"company","lineage":["https://openalex.org/I4210152613","https://openalex.org/I47646028"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Scott Smith","raw_affiliation_strings":["Maxim Integrated Products, India","Maxim Integrated"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Maxim Integrated Products, India","institution_ids":[]},{"raw_affiliation_string":"Maxim Integrated","institution_ids":["https://openalex.org/I47646028"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068067301","display_name":"Henry B. So","orcid":null},"institutions":[{"id":"https://openalex.org/I47646028","display_name":"Maxim Integrated (United Kingdom)","ror":"https://ror.org/004b7jc50","country_code":"GB","type":"company","lineage":["https://openalex.org/I4210152613","https://openalex.org/I47646028"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Henry So","raw_affiliation_strings":["Maxim Integrated Products, India","Maxim Integrated"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Maxim Integrated Products, India","institution_ids":[]},{"raw_affiliation_string":"Maxim Integrated","institution_ids":["https://openalex.org/I47646028"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I47646028"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.05742968,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"265","last_page":"270"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.6983145475387573},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.6467711925506592},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.616235077381134},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.6090017557144165},{"id":"https://openalex.org/keywords/characterization","display_name":"Characterization (materials science)","score":0.5247421860694885},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.5045245885848999},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.45387473702430725},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4421626925468445},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4245261549949646},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3957812488079071},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.27291440963745117},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.23468506336212158},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.22861328721046448},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22797232866287231},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.15504023432731628},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.15478700399398804},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.13341617584228516},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0727551281452179}],"concepts":[{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.6983145475387573},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.6467711925506592},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.616235077381134},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.6090017557144165},{"id":"https://openalex.org/C2780841128","wikidata":"https://www.wikidata.org/wiki/Q5073781","display_name":"Characterization (materials science)","level":2,"score":0.5247421860694885},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.5045245885848999},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.45387473702430725},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4421626925468445},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4245261549949646},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3957812488079071},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.27291440963745117},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.23468506336212158},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.22861328721046448},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22797232866287231},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.15504023432731628},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.15478700399398804},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.13341617584228516},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0727551281452179},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C171250308","wikidata":"https://www.wikidata.org/wiki/Q11468","display_name":"Nanotechnology","level":1,"score":0.0},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/socc.2012.6398359","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2012.6398359","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International SOC Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1988813737","https://openalex.org/W2077380902","https://openalex.org/W2117707555","https://openalex.org/W2118087362","https://openalex.org/W2118204515","https://openalex.org/W2138258502","https://openalex.org/W2142655319","https://openalex.org/W2149280425","https://openalex.org/W2293837652","https://openalex.org/W4206034126","https://openalex.org/W4248115085"],"related_works":["https://openalex.org/W1576949837","https://openalex.org/W2097523295","https://openalex.org/W4360861688","https://openalex.org/W3134930219","https://openalex.org/W984417604","https://openalex.org/W2967785526","https://openalex.org/W2908000842","https://openalex.org/W2065391525","https://openalex.org/W2113001378","https://openalex.org/W2075810349"],"abstract_inverted_index":{"To":[0],"address":[1],"timing":[2,42],"closure,":[3],"interface":[4,22],"characterization":[5,23],"and":[6,37,49,65],"power":[7,34],"problems":[8],"during":[9],"test,":[10],"a":[11],"DFT":[12],"architecture":[13],"is":[14,24,35,43],"presented":[15],"for":[16],"Multi-Clock":[17],"designs.":[18],"Results":[19],"show":[20],"that":[21,32,38],"now":[25],"able":[26],"to":[27,57,62],"be":[28],"completed":[29],"with":[30],"ATPG,":[31],"test":[33],"programmable,":[36],"ATPG":[39],"capture":[40],"clock":[41,59],"unneeded.":[44],"Current":[45],"implementations":[46],"include":[47],"65nm":[48],"40nm":[50],"Multi-Media":[51],"Compression":[52],"IC's":[53],"consisting":[54],"of":[55],"18":[56],"46":[58],"domains,":[60],"four":[61],"eight":[63],"PLL's,":[64],"several":[66],"external":[67],"interfaces.":[68]},"counts_by_year":[],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}