{"id":"https://openalex.org/W2065734352","doi":"https://doi.org/10.1109/socc.2012.6398339","title":"Calibration of propagation delay of flip-flops","display_name":"Calibration of propagation delay of flip-flops","publication_year":2012,"publication_date":"2012-09-01","ids":{"openalex":"https://openalex.org/W2065734352","doi":"https://doi.org/10.1109/socc.2012.6398339","mag":"2065734352"},"language":"en","primary_location":{"id":"doi:10.1109/socc.2012.6398339","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2012.6398339","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International SOC Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109152866","display_name":"Tamer Ragheb","orcid":null},"institutions":[{"id":"https://openalex.org/I74760111","display_name":"Texas Instruments (United States)","ror":"https://ror.org/03vsmv677","country_code":"US","type":"company","lineage":["https://openalex.org/I74760111"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tamer Ragheb","raw_affiliation_strings":["Advanced CMOS Technology Development, Texas Instruments Inc., Dallas, TX, USA","Texas Instruments, Advanced CMOS Technology Development, 13121 TI Boulevard, Dallas, TX 75243, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced CMOS Technology Development, Texas Instruments Inc., Dallas, TX, USA","institution_ids":["https://openalex.org/I74760111"]},{"raw_affiliation_string":"Texas Instruments, Advanced CMOS Technology Development, 13121 TI Boulevard, Dallas, TX 75243, USA","institution_ids":["https://openalex.org/I74760111"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5037689313","display_name":"Andrew Marshall","orcid":"https://orcid.org/0000-0001-5653-7059"},"institutions":[{"id":"https://openalex.org/I74760111","display_name":"Texas Instruments (United States)","ror":"https://ror.org/03vsmv677","country_code":"US","type":"company","lineage":["https://openalex.org/I74760111"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Andrew Marshall","raw_affiliation_strings":["Advanced CMOS Technology Development, Texas Instruments Inc., Dallas, TX, USA","Texas Instruments, Advanced CMOS Technology Development, 13121 TI Boulevard, Dallas, TX 75243, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced CMOS Technology Development, Texas Instruments Inc., Dallas, TX, USA","institution_ids":["https://openalex.org/I74760111"]},{"raw_affiliation_string":"Texas Instruments, Advanced CMOS Technology Development, 13121 TI Boulevard, Dallas, TX 75243, USA","institution_ids":["https://openalex.org/I74760111"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I74760111"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.13086732,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"376","last_page":"380"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/flops","display_name":"FLOPS","score":0.6628454923629761},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6382726430892944},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6381482481956482},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.6120438575744629},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.5645854473114014},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.5096967220306396},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5044578313827515},{"id":"https://openalex.org/keywords/flip","display_name":"Flip","score":0.5039553046226501},{"id":"https://openalex.org/keywords/calibration","display_name":"Calibration","score":0.4935554265975952},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4844805896282196},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4475817382335663},{"id":"https://openalex.org/keywords/measure","display_name":"Measure (data warehouse)","score":0.4372294843196869},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.41257569193840027},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.26037514209747314},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.25111037492752075},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14241337776184082},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.10120627284049988},{"id":"https://openalex.org/keywords/statistics","display_name":"Statistics","score":0.07193455100059509}],"concepts":[{"id":"https://openalex.org/C3826847","wikidata":"https://www.wikidata.org/wiki/Q188768","display_name":"FLOPS","level":2,"score":0.6628454923629761},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6382726430892944},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6381482481956482},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.6120438575744629},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.5645854473114014},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.5096967220306396},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5044578313827515},{"id":"https://openalex.org/C2776591724","wikidata":"https://www.wikidata.org/wiki/Q5459651","display_name":"Flip","level":3,"score":0.5039553046226501},{"id":"https://openalex.org/C165838908","wikidata":"https://www.wikidata.org/wiki/Q736777","display_name":"Calibration","level":2,"score":0.4935554265975952},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4844805896282196},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4475817382335663},{"id":"https://openalex.org/C2780009758","wikidata":"https://www.wikidata.org/wiki/Q6804172","display_name":"Measure (data warehouse)","level":2,"score":0.4372294843196869},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.41257569193840027},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.26037514209747314},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.25111037492752075},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14241337776184082},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.10120627284049988},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.07193455100059509},{"id":"https://openalex.org/C190283241","wikidata":"https://www.wikidata.org/wiki/Q14599311","display_name":"Apoptosis","level":2,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/socc.2012.6398339","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2012.6398339","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International SOC Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W1943406714","https://openalex.org/W1974974397","https://openalex.org/W2152443753","https://openalex.org/W4232143692"],"related_works":["https://openalex.org/W221087158","https://openalex.org/W2915471777","https://openalex.org/W318263151","https://openalex.org/W3032425875","https://openalex.org/W1967921351","https://openalex.org/W2013870538","https://openalex.org/W2413132533","https://openalex.org/W2032201261","https://openalex.org/W2501260229","https://openalex.org/W2406599549"],"abstract_inverted_index":{"Although":[0],"they":[1,40],"are":[2],"a":[3,15],"relatively":[4],"small":[5],"proportion":[6],"of":[7,11,29],"the":[8,24,35],"total":[9,25],"number":[10],"logic":[12,16,31,58],"gates":[13],"in":[14,53,60],"path,":[17],"latches":[18],"and":[19,48,55,66],"flip-flops":[20,54],"add":[21],"significantly":[22],"to":[23,34,46],"timing":[26],"path":[27],"delay":[28,38],"many":[30],"paths,":[32],"due":[33],"significant":[36],"cell":[37],"time":[39],"introduce.":[41],"We":[42],"introduce":[43],"new":[44],"circuitry":[45],"isolate":[47],"accurately":[49],"measure":[50],"propagation":[51],"delays":[52],"other":[56],"non-simple":[57],"structures":[59],"use":[61],"at":[62],"45nm":[63],"process":[64],"nodes":[65],"beyond.":[67]},"counts_by_year":[{"year":2019,"cited_by_count":1}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}
