{"id":"https://openalex.org/W2084778867","doi":"https://doi.org/10.1109/socc.2011.6085133","title":"Well tapping methodologies in power-gating design","display_name":"Well tapping methodologies in power-gating design","publication_year":2011,"publication_date":"2011-09-01","ids":{"openalex":"https://openalex.org/W2084778867","doi":"https://doi.org/10.1109/socc.2011.6085133","mag":"2084778867"},"language":"en","primary_location":{"id":"doi:10.1109/socc.2011.6085133","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2011.6085133","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE International SOC Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109555920","display_name":"Kaijian Shi","orcid":null},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Kaijian Shi","raw_affiliation_strings":["Cadence Design Systems, Dallas, USA","Cadence Design Systems Dallas, USA"],"affiliations":[{"raw_affiliation_string":"Cadence Design Systems, Dallas, USA","institution_ids":["https://openalex.org/I66217453"]},{"raw_affiliation_string":"Cadence Design Systems Dallas, USA","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5052564552","display_name":"David J. Tester","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"David Tester","raw_affiliation_strings":["Structured Custom, Cambridge, UK"],"affiliations":[{"raw_affiliation_string":"Structured Custom, Cambridge, UK","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5109555920"],"corresponding_institution_ids":["https://openalex.org/I66217453"],"apc_list":null,"apc_paid":null,"fwci":0.5299,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.70751591,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"128","last_page":"131"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.8930073976516724},{"id":"https://openalex.org/keywords/tapping","display_name":"Tapping","score":0.6568180322647095},{"id":"https://openalex.org/keywords/gating","display_name":"Gating","score":0.6260172128677368},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6007834076881409},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.5849106311798096},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5512000322341919},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5217693448066711},{"id":"https://openalex.org/keywords/low-power-electronics","display_name":"Low-power electronics","score":0.5083028674125671},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.4905804693698883},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.485214501619339},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4790545701980591},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.473268985748291},{"id":"https://openalex.org/keywords/leakage-power","display_name":"Leakage power","score":0.4284311830997467},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.41816988587379456},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3131444454193115},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3084009289741516},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2911164462566376},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.26227664947509766},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.24211740493774414},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.1785190999507904},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.17247247695922852},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07387104630470276}],"concepts":[{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.8930073976516724},{"id":"https://openalex.org/C2777644245","wikidata":"https://www.wikidata.org/wiki/Q203598","display_name":"Tapping","level":2,"score":0.6568180322647095},{"id":"https://openalex.org/C194544171","wikidata":"https://www.wikidata.org/wiki/Q21105679","display_name":"Gating","level":2,"score":0.6260172128677368},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6007834076881409},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.5849106311798096},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5512000322341919},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5217693448066711},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.5083028674125671},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.4905804693698883},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.485214501619339},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4790545701980591},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.473268985748291},{"id":"https://openalex.org/C2987719587","wikidata":"https://www.wikidata.org/wiki/Q1811428","display_name":"Leakage power","level":4,"score":0.4284311830997467},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.41816988587379456},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3131444454193115},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3084009289741516},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2911164462566376},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.26227664947509766},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.24211740493774414},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.1785190999507904},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.17247247695922852},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07387104630470276},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C42407357","wikidata":"https://www.wikidata.org/wiki/Q521","display_name":"Physiology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/socc.2011.6085133","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2011.6085133","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE International SOC Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.5799999833106995,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1582019256","https://openalex.org/W2027006313","https://openalex.org/W2109797003","https://openalex.org/W2125288742","https://openalex.org/W2131862714","https://openalex.org/W2146518537","https://openalex.org/W6681898109"],"related_works":["https://openalex.org/W4244696039","https://openalex.org/W3013506364","https://openalex.org/W2938543345","https://openalex.org/W3005731895","https://openalex.org/W4255392205","https://openalex.org/W2143954265","https://openalex.org/W3208532083","https://openalex.org/W1995592656","https://openalex.org/W2008603666","https://openalex.org/W2151012509"],"abstract_inverted_index":{"65nm":[0],"and":[1,52],"beyond":[2],"CMOS":[3],"designs":[4,44],"are":[5,39],"commonly":[6],"implemented":[7],"with":[8],"\u201ctapless\u201d":[9],"library":[10],"cells":[11],"which":[12],"do":[13],"not":[14],"provide":[15],"built-in":[16],"n-well":[17],"or":[18],"substrate":[19],"taps,":[20],"improving":[21],"cell":[22,25],"density.":[23],"This":[24],"efficiency":[26],"results":[27],"in":[28],"additional":[29],"layout":[30],"complexity":[31],"for":[32,41],"power-gating":[33,43],"designs.":[34],"Three":[35],"well":[36],"tapping":[37],"methods":[38],"described":[40],"production":[42],"considering":[45],"design":[46],"schedule,":[47],"leakage":[48],"power,":[49],"chip":[50],"area":[51],"complexity.":[53]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}