{"id":"https://openalex.org/W2037950447","doi":"https://doi.org/10.1109/socc.2011.6085090","title":"A novel methodology for Multi-Project System-on-a-Chip","display_name":"A novel methodology for Multi-Project System-on-a-Chip","publication_year":2011,"publication_date":"2011-09-01","ids":{"openalex":"https://openalex.org/W2037950447","doi":"https://doi.org/10.1109/socc.2011.6085090","mag":"2037950447"},"language":"en","primary_location":{"id":"doi:10.1109/socc.2011.6085090","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2011.6085090","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE International SOC Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5039735116","display_name":"Chih-Chyau Yang","orcid":"https://orcid.org/0000-0001-6508-8160"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Chih-Chyau Yang","raw_affiliation_strings":["National Chip Implementation Center, Hsinchu, Taiwan","National Chip Implementation Center (CIC), Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Chip Implementation Center, Hsinchu, Taiwan","institution_ids":[]},{"raw_affiliation_string":"National Chip Implementation Center (CIC), Hsinchu, Taiwan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090554897","display_name":"Nien-Hsiang Chang","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Nien-Hsiang Chang","raw_affiliation_strings":["National Chip Implementation Center, Hsinchu, Taiwan","National Chip Implementation Center (CIC), Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Chip Implementation Center, Hsinchu, Taiwan","institution_ids":[]},{"raw_affiliation_string":"National Chip Implementation Center (CIC), Hsinchu, Taiwan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025762419","display_name":"Shih\u2010Lun Chen","orcid":"https://orcid.org/0000-0002-4079-9350"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Shih-Lun Chen","raw_affiliation_strings":["National Chip Implementation Center, Hsinchu, Taiwan","National Chip Implementation Center (CIC), Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Chip Implementation Center, Hsinchu, Taiwan","institution_ids":[]},{"raw_affiliation_string":"National Chip Implementation Center (CIC), Hsinchu, Taiwan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086700682","display_name":"Wei-De Chien","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Wei-De Chien","raw_affiliation_strings":["National Chip Implementation Center, Hsinchu, Taiwan","National Chip Implementation Center (CIC), Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Chip Implementation Center, Hsinchu, Taiwan","institution_ids":[]},{"raw_affiliation_string":"National Chip Implementation Center (CIC), Hsinchu, Taiwan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080379943","display_name":"Chi\u2010Shi Chen","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Chi-Shi Chen","raw_affiliation_strings":["National Chip Implementation Center, Hsinchu, Taiwan","National Chip Implementation Center (CIC), Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Chip Implementation Center, Hsinchu, Taiwan","institution_ids":[]},{"raw_affiliation_string":"National Chip Implementation Center (CIC), Hsinchu, Taiwan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103047746","display_name":"Chien\u2010Ming Wu","orcid":"https://orcid.org/0000-0001-9295-7181"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Chien-Ming Wu","raw_affiliation_strings":["National Chip Implementation Center, Hsinchu, Taiwan","National Chip Implementation Center (CIC), Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Chip Implementation Center, Hsinchu, Taiwan","institution_ids":[]},{"raw_affiliation_string":"National Chip Implementation Center (CIC), Hsinchu, Taiwan","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101901556","display_name":"Chun-Ming Huang","orcid":"https://orcid.org/0000-0001-7973-9112"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Chun-Ming Huang","raw_affiliation_strings":["National Chip Implementation Center, Hsinchu, Taiwan","National Chip Implementation Center (CIC), Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Chip Implementation Center, Hsinchu, Taiwan","institution_ids":[]},{"raw_affiliation_string":"National Chip Implementation Center (CIC), Hsinchu, Taiwan","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":7,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.2576,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.55817378,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"308","last_page":"311"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.7151861190795898},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6603567600250244},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6138841509819031},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5037283301353455},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.48901447653770447},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.4833347499370575},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.47520360350608826},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4725976586341858},{"id":"https://openalex.org/keywords/virtual-prototyping","display_name":"Virtual prototyping","score":0.4404032230377197},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.4139404892921448},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.4132336378097534},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2165985405445099},{"id":"https://openalex.org/keywords/simulation","display_name":"Simulation","score":0.1186700165271759}],"concepts":[{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.7151861190795898},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6603567600250244},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6138841509819031},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5037283301353455},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.48901447653770447},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.4833347499370575},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.47520360350608826},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4725976586341858},{"id":"https://openalex.org/C2780991453","wikidata":"https://www.wikidata.org/wiki/Q3408177","display_name":"Virtual prototyping","level":2,"score":0.4404032230377197},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.4139404892921448},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.4132336378097534},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2165985405445099},{"id":"https://openalex.org/C44154836","wikidata":"https://www.wikidata.org/wiki/Q45045","display_name":"Simulation","level":1,"score":0.1186700165271759},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/socc.2011.6085090","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2011.6085090","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE International SOC Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.6299999952316284}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1529130237","https://openalex.org/W2073906129","https://openalex.org/W2104315811","https://openalex.org/W2118339691","https://openalex.org/W2144641451","https://openalex.org/W2156203118"],"related_works":["https://openalex.org/W3011978806","https://openalex.org/W2743305891","https://openalex.org/W3205162826","https://openalex.org/W2059530328","https://openalex.org/W3207169898","https://openalex.org/W2951650892","https://openalex.org/W2094385921","https://openalex.org/W2009503188","https://openalex.org/W1596716095","https://openalex.org/W4247775847"],"abstract_inverted_index":{"In":[0,36,103],"this":[1,232],"paper,":[2],"a":[3,21,47,56,59,62,66,76,156,167],"novel":[4,233],"silicon":[5,144,182,228,234],"prototyping":[6,64,117,145,235],"methodology":[7,27],"is":[8,28,75,91,184],"presented":[9],"for":[10,93,131],"Multi-Project":[11],"System-on-a-Chip":[12],"(MP-SoC)":[13],"implementation.":[14],"For":[15],"integrating":[16],"heterogeneous":[17],"SoC":[18,26,174],"projects":[19,149,175,212],"into":[20],"single":[22],"chip,":[23],"the":[24,32,40,94,98,101,133,161,164,177,191,201,214],"current":[25],"insufficient":[29],"due":[30],"to":[31,38,110],"complexity":[33],"of":[34,42,55,97,100,124,135,147,163],"MP-SoC.":[35,102],"order":[37],"improve":[39],"robustness":[41],"MP-SoC":[43,112,136,168],"design":[44,49],"and":[45,69,79,106,128],"verification,":[46],"new":[48],"flow":[50],"was":[51,170],"developed.":[52],"It":[53],"consists":[54],"virtual":[57,73],"platform,":[58,65],"logical":[60],"implementation,":[61,68],"rapid":[63,116],"physical":[67],"testing":[70,113],"stages.":[71],"The":[72,115,142,180],"platform":[74,118],"system":[77,82,86,90],"modeling":[78],"hardware/software":[80],"co-design":[81],"by":[83,154,209,231],"using":[84],"electronic":[85],"level":[87],"(ESL).":[88],"VIP":[89],"adopted":[92],"AMBA-compliant":[95],"check":[96],"interfaces":[99],"addition,":[104],"STEAC":[105],"DFT":[107],"were":[108],"used":[109],"facilitate":[111],"integration.":[114],"called":[119],"\u201cCONCORD\u201d":[120],"which":[121],"has":[122],"characteristics":[123],"connection":[125],"flexibility,":[126],"modularization,":[127],"consistence":[129],"architecture":[130],"emulating":[132],"hardware":[134],"before":[137],"chip":[138,169,203],"being":[139],"taped":[140],"out.":[141],"total":[143,181,202],"cost":[146],"these":[148,211],"can":[150],"be":[151],"greatly":[152],"reduced":[153,230],"sharing":[155,176],"common":[157,178],"platform.":[158,179],"To":[159],"demonstrate":[160],"effectiveness":[162],"proposed":[165],"methodology,":[166],"implemented":[171],"with":[172,200],"ten":[173],"area":[183,204,229],"about":[185],"37.97mm":[186],"<sup":[187,206,222],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[188,207,223],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[189,208,224],"in":[190],"TSMC":[192],"0.13um":[193],"CMOS":[194],"generic":[195],"logic":[196],"process":[197],"technology.":[198],"Compared":[199],"129.39mm":[205],"implementing":[210],"separately,":[213],"results":[215],"show":[216],"that":[217],"there":[218],"are":[219],"91.42":[220],"mm":[221],"or":[225],"70.6":[226],"%":[227],"methodology.":[236]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}