{"id":"https://openalex.org/W1991621030","doi":"https://doi.org/10.1109/socc.2010.5784652","title":"A multi-channel frequency detection and monitoring system","display_name":"A multi-channel frequency detection and monitoring system","publication_year":2010,"publication_date":"2010-09-01","ids":{"openalex":"https://openalex.org/W1991621030","doi":"https://doi.org/10.1109/socc.2010.5784652","mag":"1991621030"},"language":"en","primary_location":{"id":"doi:10.1109/socc.2010.5784652","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2010.5784652","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"23rd IEEE International SOC Conference","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103121887","display_name":"Mohammed Abdallah","orcid":"https://orcid.org/0000-0003-1017-7443"},"institutions":[{"id":"https://openalex.org/I2799756760","display_name":"Tennessee Temple University","ror":"https://ror.org/04hdj2902","country_code":"US","type":"education","lineage":["https://openalex.org/I2799756760"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Abdallah","raw_affiliation_strings":["TTU, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"TTU, USA","institution_ids":["https://openalex.org/I2799756760"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011244363","display_name":"Omar Elkeelany","orcid":null},"institutions":[{"id":"https://openalex.org/I2799756760","display_name":"Tennessee Temple University","ror":"https://ror.org/04hdj2902","country_code":"US","type":"education","lineage":["https://openalex.org/I2799756760"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"O. Elkeelany","raw_affiliation_strings":["TTU, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"TTU, USA","institution_ids":["https://openalex.org/I2799756760"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I2799756760"],"apc_list":null,"apc_paid":null,"fwci":0.6105,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.59326476,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"25","issue":null,"first_page":"309","last_page":"312"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12941","display_name":"Embedded Systems and FPGA Design","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12941","display_name":"Embedded Systems and FPGA Design","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9886999726295471,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9785000085830688,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7742863893508911},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.70304936170578},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.661942720413208},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.6205924153327942},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5459895730018616},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5402100086212158},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.5170927047729492},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5163604021072388},{"id":"https://openalex.org/keywords/signal-processing","display_name":"Signal processing","score":0.4691174328327179},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.43207836151123047},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.40415143966674805},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.39055073261260986},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.26434963941574097},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25505417585372925},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11641466617584229}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7742863893508911},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.70304936170578},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.661942720413208},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.6205924153327942},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5459895730018616},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5402100086212158},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.5170927047729492},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5163604021072388},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.4691174328327179},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.43207836151123047},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.40415143966674805},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.39055073261260986},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.26434963941574097},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25505417585372925},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11641466617584229}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/socc.2010.5784652","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2010.5784652","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"23rd IEEE International SOC Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W321326361","https://openalex.org/W2028222957","https://openalex.org/W2042406155","https://openalex.org/W2105031839","https://openalex.org/W2111291846","https://openalex.org/W2129286652","https://openalex.org/W2137547147","https://openalex.org/W2150593711","https://openalex.org/W2516434805","https://openalex.org/W4236598278","https://openalex.org/W4285719527","https://openalex.org/W6611100146","https://openalex.org/W6661048750","https://openalex.org/W6676617047","https://openalex.org/W6679351809"],"related_works":["https://openalex.org/W2808484818","https://openalex.org/W2810427553","https://openalex.org/W2135053878","https://openalex.org/W2941434274","https://openalex.org/W2340647897","https://openalex.org/W4249632163","https://openalex.org/W1760305469","https://openalex.org/W2797161794","https://openalex.org/W2073075351","https://openalex.org/W2096938998"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"an":[3],"affordable":[4],"sophisticated":[5],"stand-alone":[6],"real-time":[7,28],"multi-channel":[8,27],"analog":[9,29],"signal":[10],"Acquisition":[11],"and":[12,15,34,133,140],"Frequency":[13],"Detection":[14],"Monitoring":[16],"(FREDM)":[17],"system":[18],"is":[19,23,44,49,57,120],"proposed.":[20],"The":[21,55,89,112],"FREDM":[22,56],"used":[24],"to":[25],"acquire":[26],"signals.":[30],"It":[31],"also":[32],"detects":[33],"monitors":[35],"their":[36],"frequencies.":[37],"Any":[38],"change":[39],"in":[40,65,71],"any":[41],"channel":[42],"frequency":[43,53],"reported.":[45],"A":[46],"proper":[47],"action":[48],"taken":[50],"place":[51],"upon":[52],"change.":[54],"hardware":[58,90],"reconfigurable.":[59],"Accordingly,":[60],"it":[61],"can":[62],"be":[63],"utilized":[64],"various":[66],"real":[67],"world":[68],"applications":[69],"especially":[70],"hazardous":[72],"environments,":[73],"or":[74],"isolated":[75],"areas,":[76],"for":[77,101],"remote":[78],"architecture":[79],"reconfiguration,":[80],"while":[81],"keeping":[82],"the":[83,86,93,98,105,117,121],"cost":[84,134],"of":[85,92,97,107,115],"device":[87,99],"low.":[88],"implementation":[91],"different":[94],"processing":[95,103],"functions":[96],"allows":[100],"high-speed":[102],"without":[104],"need":[106],"expensive":[108],"general":[109],"purpose":[110],"processors.":[111],"target":[113],"technology":[114],"implementing":[116],"proposed":[118],"design":[119],"System":[122],"on":[123],"Chip":[124],"via":[125,138],"Field":[126],"Programmable":[127],"Gate":[128],"Array":[129],"(SoC-FPGA).":[130],"Performance":[131],"evaluation":[132],"comparisons":[135],"are":[136],"shown":[137],"simulation":[139],"experiments.":[141]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
