{"id":"https://openalex.org/W2104643995","doi":"https://doi.org/10.1109/socc.2008.4641548","title":"Power/throughput/area efficient PIM-based reconfigurable array for parallel processing","display_name":"Power/throughput/area efficient PIM-based reconfigurable array for parallel processing","publication_year":2008,"publication_date":"2008-09-01","ids":{"openalex":"https://openalex.org/W2104643995","doi":"https://doi.org/10.1109/socc.2008.4641548","mag":"2104643995"},"language":"en","primary_location":{"id":"doi:10.1109/socc.2008.4641548","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2008.4641548","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International SOC Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109104631","display_name":"Sohan Purohit","orcid":null},"institutions":[{"id":"https://openalex.org/I133738476","display_name":"University of Massachusetts Lowell","ror":"https://ror.org/03hamhx47","country_code":"US","type":"education","lineage":["https://openalex.org/I133738476"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sohan Purohit","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Massachusetts, Lowell, USA","Dept. of Electr. & Comput. Eng, Univ. of Massachusetts Lowell, Lowell, MA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Massachusetts, Lowell, USA","institution_ids":["https://openalex.org/I133738476"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng, Univ. of Massachusetts Lowell, Lowell, MA","institution_ids":["https://openalex.org/I133738476"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079257666","display_name":"Sai Rahul Chalamalasetti","orcid":"https://orcid.org/0000-0001-9004-440X"},"institutions":[{"id":"https://openalex.org/I133738476","display_name":"University of Massachusetts Lowell","ror":"https://ror.org/03hamhx47","country_code":"US","type":"education","lineage":["https://openalex.org/I133738476"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sai Chalamalasetti","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Massachusetts, Lowell, USA","Dept. of Electr. & Comput. Eng, Univ. of Massachusetts Lowell, Lowell, MA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Massachusetts, Lowell, USA","institution_ids":["https://openalex.org/I133738476"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng, Univ. of Massachusetts Lowell, Lowell, MA","institution_ids":["https://openalex.org/I133738476"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062664944","display_name":"Martin Margala","orcid":"https://orcid.org/0000-0002-0034-0369"},"institutions":[{"id":"https://openalex.org/I133738476","display_name":"University of Massachusetts Lowell","ror":"https://ror.org/03hamhx47","country_code":"US","type":"education","lineage":["https://openalex.org/I133738476"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Martin Margala","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Massachusetts, Lowell, USA","Dept. of Electr. & Comput. Eng, Univ. of Massachusetts Lowell, Lowell, MA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Massachusetts, Lowell, USA","institution_ids":["https://openalex.org/I133738476"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng, Univ. of Massachusetts Lowell, Lowell, MA","institution_ids":["https://openalex.org/I133738476"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5003003043","display_name":"Pasquale Corsonello","orcid":"https://orcid.org/0000-0002-9528-1110"},"institutions":[{"id":"https://openalex.org/I45204951","display_name":"University of Calabria","ror":"https://ror.org/02rc97e94","country_code":"IT","type":"education","lineage":["https://openalex.org/I45204951"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Pasquale Corsonello","raw_affiliation_strings":["Department of Electronics, Computer Science and Systems, University of Calabria, Rende, Cosenza, Italy","Dept. of Electron., Comput. Sci. & Syst., Univ. of Calabria, Rende"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics, Computer Science and Systems, University of Calabria, Rende, Cosenza, Italy","institution_ids":["https://openalex.org/I45204951"]},{"raw_affiliation_string":"Dept. of Electron., Comput. Sci. & Syst., Univ. of Calabria, Rende","institution_ids":["https://openalex.org/I45204951"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3392,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.65299527,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"1","issue":null,"first_page":"375","last_page":"378"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.7751762866973877},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7547438144683838},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6406856775283813},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5901018381118774},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5626132488250732},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4618277847766876},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4599316418170929},{"id":"https://openalex.org/keywords/parallel-processing","display_name":"Parallel processing","score":0.4425346255302429},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4421485960483551},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.42319774627685547},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.414466917514801},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3679901957511902},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.2056293785572052},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1558564007282257},{"id":"https://openalex.org/keywords/wireless","display_name":"Wireless","score":0.11148974299430847}],"concepts":[{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.7751762866973877},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7547438144683838},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6406856775283813},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5901018381118774},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5626132488250732},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4618277847766876},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4599316418170929},{"id":"https://openalex.org/C106515295","wikidata":"https://www.wikidata.org/wiki/Q26806595","display_name":"Parallel processing","level":2,"score":0.4425346255302429},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4421485960483551},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.42319774627685547},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.414466917514801},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3679901957511902},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.2056293785572052},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1558564007282257},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.11148974299430847},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/socc.2008.4641548","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2008.4641548","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International SOC Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.75,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W2025787141","https://openalex.org/W2138968074","https://openalex.org/W2171557561","https://openalex.org/W2265317952"],"related_works":["https://openalex.org/W3014521742","https://openalex.org/W2111241003","https://openalex.org/W4200391368","https://openalex.org/W2355315220","https://openalex.org/W2617868873","https://openalex.org/W2210979487","https://openalex.org/W3204141294","https://openalex.org/W2074043759","https://openalex.org/W2026622428","https://openalex.org/W1980662701"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,52],"PIM-based":[4],"(Processing-in-Memory)":[5],"architecture":[6,15],"based":[7],"on":[8],"new":[9,29],"reconfigurable":[10,30],"cell":[11,31],"data":[12],"path.":[13],"The":[14,25],"delivers":[16],"increased":[17],"power/throughput/area":[18],"efficiency":[19],"compared":[20],"to":[21],"previous":[22],"well-known":[23],"architectures.":[24],"investigation":[26],"of":[27,44],"the":[28],"design":[32],"was":[33],"performed":[34],"in":[35],"0.18":[36],"and":[37],"0.13":[38],"micron":[39],"CMOS":[40],"technology":[41],"nodes.":[42],"Specifications":[43],"individual":[45],"blocks":[46],"are":[47],"presented":[48],"as":[49,51],"well":[50],"comparison":[53],"with":[54],"existing":[55],"designs":[56],"for":[57],"8x8":[58],"2D":[59],"DCT":[60],"application.":[61]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}