{"id":"https://openalex.org/W2099030973","doi":"https://doi.org/10.1109/socc.2008.4641528","title":"A framework of architectural synthesis for dynamically reconfigurable FPGAs","display_name":"A framework of architectural synthesis for dynamically reconfigurable FPGAs","publication_year":2008,"publication_date":"2008-09-01","ids":{"openalex":"https://openalex.org/W2099030973","doi":"https://doi.org/10.1109/socc.2008.4641528","mag":"2099030973"},"language":"en","primary_location":{"id":"doi:10.1109/socc.2008.4641528","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2008.4641528","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International SOC Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101554099","display_name":"Ting Liu","orcid":"https://orcid.org/0000-0002-7600-0934"},"institutions":[{"id":"https://openalex.org/I90183372","display_name":"Universit\u00e9 de Lorraine","ror":"https://ror.org/04vfs2w97","country_code":"FR","type":"education","lineage":["https://openalex.org/I90183372"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"Ting Liu","raw_affiliation_strings":["Laboratoire d'Instrumentation Electronique de Nancy, Universit\u00e9 Henri Poincar\u00e9 Nancy I, France"],"affiliations":[{"raw_affiliation_string":"Laboratoire d'Instrumentation Electronique de Nancy, Universit\u00e9 Henri Poincar\u00e9 Nancy I, France","institution_ids":["https://openalex.org/I90183372"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036139436","display_name":"Camel Tanougast","orcid":"https://orcid.org/0000-0002-5399-1683"},"institutions":[{"id":"https://openalex.org/I90183372","display_name":"Universit\u00e9 de Lorraine","ror":"https://ror.org/04vfs2w97","country_code":"FR","type":"education","lineage":["https://openalex.org/I90183372"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Camel Tanougast","raw_affiliation_strings":["Laboratoire d'Instrumentation Electronique de Nancy, Universit\u00e9 Henri Poincar\u00e9 Nancy I, France"],"affiliations":[{"raw_affiliation_string":"Laboratoire d'Instrumentation Electronique de Nancy, Universit\u00e9 Henri Poincar\u00e9 Nancy I, France","institution_ids":["https://openalex.org/I90183372"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5051882205","display_name":"Serge Weber","orcid":"https://orcid.org/0000-0002-7851-9916"},"institutions":[{"id":"https://openalex.org/I90183372","display_name":"Universit\u00e9 de Lorraine","ror":"https://ror.org/04vfs2w97","country_code":"FR","type":"education","lineage":["https://openalex.org/I90183372"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Serge Weber","raw_affiliation_strings":["Laboratoire d'Instrumentation Electronique de Nancy, Universit\u00e9 Henri Poincar\u00e9 Nancy I, France"],"affiliations":[{"raw_affiliation_string":"Laboratoire d'Instrumentation Electronique de Nancy, Universit\u00e9 Henri Poincar\u00e9 Nancy I, France","institution_ids":["https://openalex.org/I90183372"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5101554099"],"corresponding_institution_ids":["https://openalex.org/I90183372"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.08741041,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"27","issue":null,"first_page":"283","last_page":"286"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.8201186656951904},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7896696329116821},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6919148564338684},{"id":"https://openalex.org/keywords/partition","display_name":"Partition (number theory)","score":0.6245399713516235},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.5670168995857239},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5424594879150391},{"id":"https://openalex.org/keywords/reuse","display_name":"Reuse","score":0.5334330797195435},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.5231441259384155},{"id":"https://openalex.org/keywords/merge","display_name":"Merge (version control)","score":0.519494891166687},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.4728303849697113},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4650735855102539},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.4233020544052124},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3957030177116394},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.35764312744140625},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.16863849759101868},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09256589412689209}],"concepts":[{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.8201186656951904},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7896696329116821},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6919148564338684},{"id":"https://openalex.org/C42812","wikidata":"https://www.wikidata.org/wiki/Q1082910","display_name":"Partition (number theory)","level":2,"score":0.6245399713516235},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.5670168995857239},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5424594879150391},{"id":"https://openalex.org/C206588197","wikidata":"https://www.wikidata.org/wiki/Q846574","display_name":"Reuse","level":2,"score":0.5334330797195435},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.5231441259384155},{"id":"https://openalex.org/C197129107","wikidata":"https://www.wikidata.org/wiki/Q1921621","display_name":"Merge (version control)","level":2,"score":0.519494891166687},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.4728303849697113},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4650735855102539},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.4233020544052124},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3957030177116394},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.35764312744140625},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.16863849759101868},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09256589412689209},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C548081761","wikidata":"https://www.wikidata.org/wiki/Q180388","display_name":"Waste management","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/socc.2008.4641528","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2008.4641528","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International SOC Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W113872045","https://openalex.org/W1603444000","https://openalex.org/W1892041103","https://openalex.org/W1968241279","https://openalex.org/W2002703587","https://openalex.org/W2051924386","https://openalex.org/W2110602765","https://openalex.org/W2113913528","https://openalex.org/W2155742588","https://openalex.org/W2155826582","https://openalex.org/W2539152084","https://openalex.org/W4230946966"],"related_works":["https://openalex.org/W2204754129","https://openalex.org/W4322751528","https://openalex.org/W2759209791","https://openalex.org/W2169571474","https://openalex.org/W2340647897","https://openalex.org/W2500205862","https://openalex.org/W2760049414","https://openalex.org/W1569711686","https://openalex.org/W1541284233","https://openalex.org/W2808484818"],"abstract_inverted_index":{"Reconfiguration":[0],"latency":[1],"is":[2,21,122],"an":[3,29,148],"important":[4],"factor":[5],"which":[6],"impacts":[7],"the":[8,12,42,53,57,61,68,75,86,89,108,111,116,130,133,152],"system":[9],"performance":[10],"in":[11,151],"reconfigurable":[13,37,153],"computing":[14],"design.":[15,154],"In":[16],"this":[17,126],"paper,":[18],"a":[19,25,47,64,81,95,99],"framework":[20],"proposed":[22,103],"that":[23,142],"presents":[24],"novel":[26,127],"approach":[27,79,104],"for":[28,94,114,147],"optimal":[30],"implementation":[31,62,97,150],"of":[32,63,74,88,110,135],"algorithms":[33],"on":[34,72,85],"FPGA":[35],"based":[36,71,84],"system.":[38],"The":[39,102,139],"method":[40],"optimizes":[41],"temporal":[43,112],"partitioning":[44],"by":[45,67],"performing":[46],"similar-rate-computing-based":[48],"architectural":[49,69,131],"synthesis.":[50],"It":[51],"gives":[52],"possibility":[54],"to":[55,106,124],"merge":[56],"related":[58],"partitions":[59,113],"during":[60],"target":[65],"architecture":[66],"synthesis":[70,100],"reusing":[73],"common":[76],"task.":[77],"Our":[78],"proposes":[80],"final":[82],"solution":[83],"computation":[87],"mutual":[90],"similar":[91],"rate":[92],"(M.S.R.)":[93],"RTR":[96],"with":[98],"option.":[101],"attempts":[105],"reduce":[107],"number":[109,134],"minimizing":[115],"overall":[117],"execution":[118],"time.":[119],"An":[120],"example":[121],"presented":[123],"illustrate":[125],"approach.":[128],"With":[129],"synthesis,":[132],"partition":[136],"was":[137],"decreased.":[138],"results":[140],"demonstrate":[141],"are":[143],"capable":[144],"and":[145],"efficient":[146],"optimized":[149]},"counts_by_year":[{"year":2020,"cited_by_count":2},{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
