{"id":"https://openalex.org/W2160953128","doi":"https://doi.org/10.1109/socc.2008.4641486","title":"A systematic approach to synthesis of verification test-suites for modular SoC designs","display_name":"A systematic approach to synthesis of verification test-suites for modular SoC designs","publication_year":2008,"publication_date":"2008-09-01","ids":{"openalex":"https://openalex.org/W2160953128","doi":"https://doi.org/10.1109/socc.2008.4641486","mag":"2160953128"},"language":"en","primary_location":{"id":"doi:10.1109/socc.2008.4641486","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2008.4641486","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International SOC Conference","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5040810102","display_name":"Sudhakar Surendran","orcid":null},"institutions":[{"id":"https://openalex.org/I74760111","display_name":"Texas Instruments (United States)","ror":"https://ror.org/03vsmv677","country_code":"US","type":"company","lineage":["https://openalex.org/I74760111"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sudhakar Surendran","raw_affiliation_strings":["Camera Phone Business Unit, Texas Instruments (India) Private Limited, Bangalore, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Camera Phone Business Unit, Texas Instruments (India) Private Limited, Bangalore, India","institution_ids":["https://openalex.org/I74760111"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028519358","display_name":"Rubin Parekhji","orcid":"https://orcid.org/0009-0000-6625-2786"},"institutions":[{"id":"https://openalex.org/I74760111","display_name":"Texas Instruments (United States)","ror":"https://ror.org/03vsmv677","country_code":"US","type":"company","lineage":["https://openalex.org/I74760111"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rubin Parekhji","raw_affiliation_strings":["SoC Design Technology Center, Texas Instruments (India) Private Limited, Bangalore, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"SoC Design Technology Center, Texas Instruments (India) Private Limited, Bangalore, India","institution_ids":["https://openalex.org/I74760111"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5113510967","display_name":"R. Govindarajan","orcid":null},"institutions":[{"id":"https://openalex.org/I59270414","display_name":"Indian Institute of Science Bangalore","ror":"https://ror.org/04dese585","country_code":"IN","type":"education","lineage":["https://openalex.org/I59270414"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"R. Govindarajan","raw_affiliation_strings":["Super Computer Edn. and Research Center, Indian Institute of Science, Bangalore, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Super Computer Edn. and Research Center, Indian Institute of Science, Bangalore, India","institution_ids":["https://openalex.org/I59270414"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"91","last_page":"96"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7600876092910767},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.747199535369873},{"id":"https://openalex.org/keywords/functional-verification","display_name":"Functional verification","score":0.6292850375175476},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5826807618141174},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5749138593673706},{"id":"https://openalex.org/keywords/intelligent-verification","display_name":"Intelligent verification","score":0.5434468388557434},{"id":"https://openalex.org/keywords/software-verification","display_name":"Software verification","score":0.45570218563079834},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.4423050284385681},{"id":"https://openalex.org/keywords/test","display_name":"Test (biology)","score":0.42652079463005066},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4039709270000458},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.38230156898498535},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.2437560260295868},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15295130014419556},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.12712574005126953},{"id":"https://openalex.org/keywords/software-construction","display_name":"Software construction","score":0.07015827298164368},{"id":"https://openalex.org/keywords/software-system","display_name":"Software system","score":0.06262493133544922}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7600876092910767},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.747199535369873},{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.6292850375175476},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5826807618141174},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5749138593673706},{"id":"https://openalex.org/C3406870","wikidata":"https://www.wikidata.org/wiki/Q6044160","display_name":"Intelligent verification","level":5,"score":0.5434468388557434},{"id":"https://openalex.org/C33054407","wikidata":"https://www.wikidata.org/wiki/Q6504747","display_name":"Software verification","level":5,"score":0.45570218563079834},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.4423050284385681},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.42652079463005066},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4039709270000458},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.38230156898498535},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.2437560260295868},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15295130014419556},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.12712574005126953},{"id":"https://openalex.org/C186846655","wikidata":"https://www.wikidata.org/wiki/Q3398377","display_name":"Software construction","level":4,"score":0.07015827298164368},{"id":"https://openalex.org/C149091818","wikidata":"https://www.wikidata.org/wiki/Q2429814","display_name":"Software system","level":3,"score":0.06262493133544922},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/socc.2008.4641486","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2008.4641486","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International SOC Conference","raw_type":"proceedings-article"},{"id":"pmh:oai:eprints.iisc.ac.in:40723","is_oa":false,"landing_page_url":null,"pdf_url":null,"source":{"id":"https://openalex.org/S4377196309","display_name":"NOT FOUND REPOSITORY (Indian Institute of Science Bangalore)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I59270414","host_organization_name":"Indian Institute of Science Bangalore","host_organization_lineage":["https://openalex.org/I59270414"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"acceptedVersion","is_accepted":true,"is_published":false,"raw_source_name":"","raw_type":"Conference Paper"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5099999904632568,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1541510538","https://openalex.org/W1555915743","https://openalex.org/W1566072248","https://openalex.org/W1582770309","https://openalex.org/W2123843480","https://openalex.org/W2154893317","https://openalex.org/W2156208763","https://openalex.org/W2157024459","https://openalex.org/W2160289783","https://openalex.org/W2613359208","https://openalex.org/W2972167349","https://openalex.org/W3174107850","https://openalex.org/W4249857531","https://openalex.org/W6682860722"],"related_works":["https://openalex.org/W3120172095","https://openalex.org/W1985271980","https://openalex.org/W3036403349","https://openalex.org/W2118572231","https://openalex.org/W2108860137","https://openalex.org/W1563456403","https://openalex.org/W2013077575","https://openalex.org/W4375946032","https://openalex.org/W2535719568","https://openalex.org/W2138343703"],"abstract_inverted_index":{"Verification":[0],"is":[1,60],"one":[2,49],"of":[3,18,38,44],"the":[4,19,58],"important":[5],"stages":[6],"in":[7],"designing":[8],"an":[9],"SoC":[10,50],"(system":[11],"on":[12],"chips)":[13],"that":[14],"consumes":[15],"upto":[16],"70%":[17],"design":[20],"time.":[21],"In":[22],"this":[23],"work,":[24],"we":[25],"present":[26],"a":[27,36],"methodology":[28],"to":[29,34,51],"automatically":[30],"generate":[31],"verification":[32,45],"test-cases":[33,59],"verify":[35],"class":[37],"SoCs":[39],"and":[40],"also":[41,61],"enable":[42],"re-use":[43],"resources":[46],"created":[47],"from":[48],"another.":[52],"A":[53],"prototype":[54],"implementation":[55],"for":[56],"generating":[57],"presented.":[62]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}