{"id":"https://openalex.org/W2156440263","doi":"https://doi.org/10.1109/socc.2008.4641472","title":"The role of interconnects in the performance scalability of multicore architectures","display_name":"The role of interconnects in the performance scalability of multicore architectures","publication_year":2008,"publication_date":"2008-09-01","ids":{"openalex":"https://openalex.org/W2156440263","doi":"https://doi.org/10.1109/socc.2008.4641472","mag":"2156440263"},"language":"en","primary_location":{"id":"doi:10.1109/socc.2008.4641472","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2008.4641472","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International SOC Conference","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5059524537","display_name":"Jiangjiang Liu","orcid":"https://orcid.org/0000-0002-1341-2763"},"institutions":[{"id":"https://openalex.org/I177898655","display_name":"Lamar University","ror":"https://ror.org/008ms5s18","country_code":"US","type":"education","lineage":["https://openalex.org/I177898655"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jiangjiang Liu","raw_affiliation_strings":["Department of Computer Science, Lamar University, Beaumont, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Lamar University, Beaumont, TX, USA","institution_ids":["https://openalex.org/I177898655"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108624212","display_name":"Nihar R. Mahapatra","orcid":"https://orcid.org/0000-0002-3821-3330"},"institutions":[{"id":"https://openalex.org/I87216513","display_name":"Michigan State University","ror":"https://ror.org/05hs6h993","country_code":"US","type":"education","lineage":["https://openalex.org/I87216513"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nihar R. Mahapatra","raw_affiliation_strings":["Department of Electrical & Computer Engineering, Michigan State University, East Lansing, MI, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical & Computer Engineering, Michigan State University, East Lansing, MI, USA","institution_ids":["https://openalex.org/I87216513"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.17771261,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"21","last_page":"24"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.8022882342338562},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7966181039810181},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.654822051525116},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.581763505935669},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5317177772521973},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.5201890468597412},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4880896806716919},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4560326635837555},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.4529995322227478},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.45067504048347473},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.44433802366256714},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.4410313069820404},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4349902272224426},{"id":"https://openalex.org/keywords/spec#","display_name":"Spec#","score":0.41168567538261414},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3357927203178406},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.18050146102905273},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10831466317176819},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09032967686653137},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.07828152179718018}],"concepts":[{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.8022882342338562},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7966181039810181},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.654822051525116},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.581763505935669},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5317177772521973},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.5201890468597412},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4880896806716919},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4560326635837555},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.4529995322227478},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.45067504048347473},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.44433802366256714},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.4410313069820404},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4349902272224426},{"id":"https://openalex.org/C2778565505","wikidata":"https://www.wikidata.org/wiki/Q2207566","display_name":"Spec#","level":2,"score":0.41168567538261414},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3357927203178406},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.18050146102905273},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10831466317176819},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09032967686653137},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.07828152179718018},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/socc.2008.4641472","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2008.4641472","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International SOC Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1983242583","https://openalex.org/W2044206819","https://openalex.org/W2098156582","https://openalex.org/W2117324528","https://openalex.org/W2150121003","https://openalex.org/W4248800093"],"related_works":["https://openalex.org/W878150521","https://openalex.org/W2008941207","https://openalex.org/W2373662841","https://openalex.org/W1970478390","https://openalex.org/W1533638723","https://openalex.org/W294916044","https://openalex.org/W2131667412","https://openalex.org/W4248631090","https://openalex.org/W2031026393","https://openalex.org/W2063611263"],"abstract_inverted_index":{"In":[0],"this":[1,32],"paper,":[2],"we":[3],"investigate":[4],"how":[5],"the":[6,15,18,28,68,80,89,95],"interconnects":[7],"used":[8],"for":[9],"instruction":[10],"and":[11,17,63,94],"data":[12],"communication":[13],"between":[14],"cores":[16],"memory":[19,47],"system":[20],"limit":[21],"multi-core":[22,84],"chip":[23,85],"performance":[24,86],"scalability.":[25],"We":[26,70],"show":[27],"extent":[29],"to":[30],"which":[31],"limitation":[33],"can":[34],"be":[35],"alleviated":[36],"by:":[37],"(1)":[38],"using":[39,53],"a":[40,65,74],"simple":[41],"thread":[42],"scheduling":[43],"approach":[44,82,91],"that":[45,58],"balances":[46],"access":[48],"demands":[49],"across":[50,73],"cores,":[51],"(2)":[52],"techniques":[54],"(such":[55],"as":[56],"compression)":[57],"improve":[59],"effective":[60],"interconnect":[61],"bandwidth,":[62],"(3)":[64],"combination":[66],"of":[67,76],"two.":[69],"find":[71],"that,":[72],"range":[75],"SPEC":[77],"CINT2000":[78],"programs,":[79],"first":[81],"improves":[83],"by":[87,92,97],"14.99%\u201333.31%,":[88],"second":[90],"22.28%\u201364.43%,":[93],"third":[96],"33.97%\u201387.92%.":[98]},"counts_by_year":[{"year":2018,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}