{"id":"https://openalex.org/W1539534578","doi":"https://doi.org/10.1109/socc.2005.1554510","title":"A hierarchically-controlled simd machine for 2D DCT on FPGAs","display_name":"A hierarchically-controlled simd machine for 2D DCT on FPGAs","publication_year":2005,"publication_date":"2005-12-13","ids":{"openalex":"https://openalex.org/W1539534578","doi":"https://doi.org/10.1109/socc.2005.1554510","mag":"1539534578"},"language":"en","primary_location":{"id":"doi:10.1109/socc.2005.1554510","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2005.1554510","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 Joint 30th International Conference on Infrared and Millimeter Waves and 13th International Conference on Terahertz Electronics","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5087200028","display_name":"Xizhen Xu","orcid":null},"institutions":[{"id":"https://openalex.org/I118118575","display_name":"New Jersey Institute of Technology","ror":"https://ror.org/05e74xb87","country_code":"US","type":"education","lineage":["https://openalex.org/I118118575"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Xizhen Xu","raw_affiliation_strings":["Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, NJ, USA","Dept. of Electr. & Comput. Eng., New Jersey Inst. of Tech., Newark, NJ, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, NJ, USA","institution_ids":["https://openalex.org/I118118575"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., New Jersey Inst. of Tech., Newark, NJ, USA","institution_ids":["https://openalex.org/I118118575"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5076762145","display_name":"Sotirios G. Ziavras","orcid":"https://orcid.org/0000-0002-3764-1528"},"institutions":[{"id":"https://openalex.org/I118118575","display_name":"New Jersey Institute of Technology","ror":"https://ror.org/05e74xb87","country_code":"US","type":"education","lineage":["https://openalex.org/I118118575"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S.G. Ziavras","raw_affiliation_strings":["Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, NJ, USA","Dept. of Electr. & Comput. Eng., New Jersey Inst. of Tech., Newark, NJ, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, NJ, USA","institution_ids":["https://openalex.org/I118118575"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., New Jersey Inst. of Tech., Newark, NJ, USA","institution_ids":["https://openalex.org/I118118575"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5087200028"],"corresponding_institution_ids":["https://openalex.org/I118118575"],"apc_list":null,"apc_paid":null,"fwci":1.289,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.80367772,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"276","last_page":"279"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9932000041007996,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8270338773727417},{"id":"https://openalex.org/keywords/simd","display_name":"SIMD","score":0.7496839761734009},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7242098450660706},{"id":"https://openalex.org/keywords/bottleneck","display_name":"Bottleneck","score":0.7068989276885986},{"id":"https://openalex.org/keywords/coprocessor","display_name":"Coprocessor","score":0.6931840181350708},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5229414701461792},{"id":"https://openalex.org/keywords/workstation","display_name":"Workstation","score":0.48375391960144043},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4804786741733551},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4682620167732239},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.4558417499065399},{"id":"https://openalex.org/keywords/discrete-cosine-transform","display_name":"Discrete cosine transform","score":0.4345740079879761},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.4259750247001648},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.11640939116477966},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.09941262006759644}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8270338773727417},{"id":"https://openalex.org/C150552126","wikidata":"https://www.wikidata.org/wiki/Q339387","display_name":"SIMD","level":2,"score":0.7496839761734009},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7242098450660706},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.7068989276885986},{"id":"https://openalex.org/C86111242","wikidata":"https://www.wikidata.org/wiki/Q859595","display_name":"Coprocessor","level":2,"score":0.6931840181350708},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5229414701461792},{"id":"https://openalex.org/C67953723","wikidata":"https://www.wikidata.org/wiki/Q192525","display_name":"Workstation","level":2,"score":0.48375391960144043},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4804786741733551},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4682620167732239},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.4558417499065399},{"id":"https://openalex.org/C2221639","wikidata":"https://www.wikidata.org/wiki/Q2877","display_name":"Discrete cosine transform","level":3,"score":0.4345740079879761},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.4259750247001648},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.11640939116477966},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.09941262006759644},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/socc.2005.1554510","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2005.1554510","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 Joint 30th International Conference on Infrared and Millimeter Waves and 13th International Conference on Terahertz Electronics","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.62.6901","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.62.6901","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://web.njit.edu/~ziavras/socc2005-1.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4300000071525574,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1885706698","https://openalex.org/W2039870651","https://openalex.org/W2109218940","https://openalex.org/W2131959641","https://openalex.org/W2148248162"],"related_works":["https://openalex.org/W2595172197","https://openalex.org/W2084856301","https://openalex.org/W2127970246","https://openalex.org/W1001352512","https://openalex.org/W2108180358","https://openalex.org/W2987731717","https://openalex.org/W2393747601","https://openalex.org/W2796337470","https://openalex.org/W2120385681","https://openalex.org/W2171605838"],"abstract_inverted_index":{"Platform":[0],"FPGA":[1,79],"devices":[2],"are":[3],"an":[4,41,78],"attractive":[5],"option":[6],"for":[7],"implementing":[8],"parallel":[9],"systems":[10],"on":[11],"a":[12,20,35,47,57,67,90],"single":[13],"chip":[14],"that":[15],"can":[16],"be":[17],"used":[18],"as":[19,99,101],"coprocessor.":[21],"However,":[22],"the":[23,28,32,115,118],"substantial":[24],"communication":[25],"overhead":[26],"between":[27],"host":[29],"workstation":[30],"and":[31],"FPGAs":[33,44],"is":[34,111],"major":[36],"performance":[37],"bottleneck.":[38],"Also,":[39],"mapping":[40],"application":[42],"to":[43,81,94,113],"still":[45],"remains":[46],"daunting":[48],"job.":[49],"To":[50],"address":[51],"these":[52],"problems,":[53],"this":[54],"paper":[55],"describes":[56],"hierarchical":[58,68],"SIMD":[59],"(H-SIMD)":[60],"machine":[61],"design":[62,76],"with":[63,97],"its":[64],"codesign":[65],"of":[66,84,117],"instruction":[69],"set":[70],"architecture":[71],"(HISA).":[72],"The":[73,103],"proposed":[74],"H-SIMD":[75,119],"uses":[77],"controller":[80],"facilitate":[82],"ease":[83],"program":[85],"development.":[86],"It":[87],"also":[88],"employs":[89],"memory":[91],"switching":[92],"scheme":[93],"overlap":[95],"communications":[96],"computations":[98],"much":[100],"possible.":[102],"two-dimensional":[104],"discrete":[105],"cosine":[106],"transform":[107],"(DCT2":[108],"or":[109],"2D-DCT)":[110],"enlisted":[112],"show":[114],"effectiveness":[116],"machine.":[120]},"counts_by_year":[{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}