{"id":"https://openalex.org/W1521460611","doi":"https://doi.org/10.1109/socc.2004.1362348","title":"Transparent SOC: on-chip analyzing techniques and implementation for embedded processor","display_name":"Transparent SOC: on-chip analyzing techniques and implementation for embedded processor","publication_year":2004,"publication_date":"2004-12-23","ids":{"openalex":"https://openalex.org/W1521460611","doi":"https://doi.org/10.1109/socc.2004.1362348","mag":"1521460611"},"language":"en","primary_location":{"id":"doi:10.1109/socc.2004.1362348","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2004.1362348","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE International SOC Conference, 2004. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5038860581","display_name":"Makoto Saen","orcid":null},"institutions":[{"id":"https://openalex.org/I65143321","display_name":"Hitachi (Japan)","ror":"https://ror.org/02exqgm79","country_code":"JP","type":"company","lineage":["https://openalex.org/I65143321"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"M. Saen","raw_affiliation_strings":["Hitachi and Limited, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Hitachi and Limited, Tokyo, Japan","institution_ids":["https://openalex.org/I65143321"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079923859","display_name":"M. Nakagawa","orcid":null},"institutions":[{"id":"https://openalex.org/I4210153176","display_name":"Renesas Electronics (Japan)","ror":"https://ror.org/058wb7691","country_code":"JP","type":"company","lineage":["https://openalex.org/I4210153176"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"M. Nakagawa","raw_affiliation_strings":["Renesas Technology Corporation, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Renesas Technology Corporation, Tokyo, Japan","institution_ids":["https://openalex.org/I4210153176"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085085391","display_name":"J. Nishimoto","orcid":null},"institutions":[{"id":"https://openalex.org/I4210153176","display_name":"Renesas Electronics (Japan)","ror":"https://ror.org/058wb7691","country_code":"JP","type":"company","lineage":["https://openalex.org/I4210153176"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"J. Nishimoto","raw_affiliation_strings":["Renesas Technology Corporation, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Renesas Technology Corporation, Tokyo, Japan","institution_ids":["https://openalex.org/I4210153176"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056831192","display_name":"Tetsuya Kodama","orcid":"https://orcid.org/0000-0003-4727-9558"},"institutions":[{"id":"https://openalex.org/I65143321","display_name":"Hitachi (Japan)","ror":"https://ror.org/02exqgm79","country_code":"JP","type":"company","lineage":["https://openalex.org/I65143321"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"T. Kodama","raw_affiliation_strings":["Hitachi and Limited, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Hitachi and Limited, Tokyo, Japan","institution_ids":["https://openalex.org/I65143321"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112732930","display_name":"F. Arakawa","orcid":null},"institutions":[{"id":"https://openalex.org/I65143321","display_name":"Hitachi (Japan)","ror":"https://ror.org/02exqgm79","country_code":"JP","type":"company","lineage":["https://openalex.org/I65143321"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"F. Arakawa","raw_affiliation_strings":["Hitachi and Limited, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Hitachi and Limited, Tokyo, Japan","institution_ids":["https://openalex.org/I65143321"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5038860581"],"corresponding_institution_ids":["https://openalex.org/I65143321"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.06146418,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"16","issue":null,"first_page":"51","last_page":"54"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8116191625595093},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.7374875545501709},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.6831040978431702},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6085940599441528},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.5833644270896912},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5691481828689575},{"id":"https://openalex.org/keywords/encoding","display_name":"Encoding (memory)","score":0.46754875779151917},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4645272195339203},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.399223655462265},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3965945839881897},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12058112025260925},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.08933264017105103},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.07095253467559814}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8116191625595093},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.7374875545501709},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.6831040978431702},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6085940599441528},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.5833644270896912},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5691481828689575},{"id":"https://openalex.org/C125411270","wikidata":"https://www.wikidata.org/wiki/Q18653","display_name":"Encoding (memory)","level":2,"score":0.46754875779151917},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4645272195339203},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.399223655462265},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3965945839881897},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12058112025260925},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.08933264017105103},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.07095253467559814},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/socc.2004.1362348","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc.2004.1362348","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE International SOC Conference, 2004. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1541963660","https://openalex.org/W1554340369","https://openalex.org/W1595098459","https://openalex.org/W2099552425","https://openalex.org/W2108202121","https://openalex.org/W2121864144","https://openalex.org/W2165951240","https://openalex.org/W4251840223","https://openalex.org/W6677959934"],"related_works":["https://openalex.org/W2355022049","https://openalex.org/W2060429446","https://openalex.org/W2380573388","https://openalex.org/W2741782512","https://openalex.org/W2369636957","https://openalex.org/W3011302839","https://openalex.org/W2392958391","https://openalex.org/W2065289416","https://openalex.org/W2017236304","https://openalex.org/W2115579119"],"abstract_inverted_index":{"An":[0],"on-chip":[1],"analysis":[2,23,41,72],"technique":[3,19,99],"for":[4,40,63],"SOC,":[5],"which":[6,37],"enables":[7,73],"system":[8,77],"performance":[9,78],"to":[10,17,49,75],"be":[11,50,112],"improved,":[12],"was":[13,87],"developed.":[14],"The":[15],"key":[16],"this":[18,71,98,120],"is":[20,29,100,105],"the":[21,25,47,90,115],"synchronized":[22],"of":[24],"whole":[26],"SOC.":[27],"This":[28],"made":[30],"possible":[31],"by":[32,79,118],"a":[33,59],"circuit":[34],"structure":[35],"in":[36,56],"small":[38],"circuits":[39,54],"are":[42],"distributed":[43],"at":[44],"points":[45],"on":[46,93],"SOC":[48,108],"analyzed,":[51],"and":[52],"these":[53],"operate":[55],"synchronization":[57],"through":[58],"special":[60],"network.":[61],"Benchmarks":[62],"multimedia":[64],"operations":[65],"(including":[66],"MPEG":[67],"encoding)":[68],"show":[69],"that":[70,89,107],"us":[74],"improve":[76],"17%":[80],"with":[81],"minimum":[82],"trial-and-error.":[83],"In":[84],"addition,":[85],"it":[86,104],"confirmed":[88],"negative":[91],"impact":[92],"chip":[94],"area":[95],"when":[96],"applying":[97],"very":[101],"small.":[102],"And":[103],"concluded":[106],"design":[109],"time":[110],"can":[111],"shortened":[113],"during":[114],"system-development":[116],"stage":[117],"using":[119],"technique.":[121]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
