{"id":"https://openalex.org/W4386066988","doi":"https://doi.org/10.1109/smartnets58706.2023.10215714","title":"FPGA-based tunable Keccak core","display_name":"FPGA-based tunable Keccak core","publication_year":2023,"publication_date":"2023-07-25","ids":{"openalex":"https://openalex.org/W4386066988","doi":"https://doi.org/10.1109/smartnets58706.2023.10215714"},"language":"en","primary_location":{"id":"doi:10.1109/smartnets58706.2023.10215714","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/smartnets58706.2023.10215714","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 International Conference on Smart Applications, Communications and Networking (SmartNets)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000379265","display_name":"Ahmed Maache","orcid":null},"institutions":[{"id":"https://openalex.org/I3121272148","display_name":"University of Boumerdes","ror":"https://ror.org/02dveg925","country_code":"DZ","type":"education","lineage":["https://openalex.org/I3121272148"]}],"countries":["DZ"],"is_corresponding":true,"raw_author_name":"Ahmed Maache","raw_affiliation_strings":["University M&#x2019;Hamed Bougara of Boumerdes,Laboratory of Signals and Systems, Institute of Electrical Engineering and Electronics,Algeria"],"affiliations":[{"raw_affiliation_string":"University M&#x2019;Hamed Bougara of Boumerdes,Laboratory of Signals and Systems, Institute of Electrical Engineering and Electronics,Algeria","institution_ids":["https://openalex.org/I3121272148"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5035543074","display_name":"Abdesattar Kalache","orcid":"https://orcid.org/0000-0002-5560-3250"},"institutions":[{"id":"https://openalex.org/I3121272148","display_name":"University of Boumerdes","ror":"https://ror.org/02dveg925","country_code":"DZ","type":"education","lineage":["https://openalex.org/I3121272148"]}],"countries":["DZ"],"is_corresponding":false,"raw_author_name":"Abdesattar Kalache","raw_affiliation_strings":["University M&#x2019;Hamed Bougara of Boumerdes,Laboratory of Signals and Systems, Institute of Electrical Engineering and Electronics,Algeria"],"affiliations":[{"raw_affiliation_string":"University M&#x2019;Hamed Bougara of Boumerdes,Laboratory of Signals and Systems, Institute of Electrical Engineering and Electronics,Algeria","institution_ids":["https://openalex.org/I3121272148"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5000379265"],"corresponding_institution_ids":["https://openalex.org/I3121272148"],"apc_list":null,"apc_paid":null,"fwci":0.1228,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.40521161,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"2","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11017","display_name":"Chaos-based Image/Signal Encryption","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11017","display_name":"Chaos-based Image/Signal Encryption","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12162","display_name":"Cellular Automata and Applications","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7705032229423523},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6421206593513489},{"id":"https://openalex.org/keywords/core","display_name":"Core (optical fiber)","score":0.5835827589035034},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.44351664185523987},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.39895516633987427},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.23211663961410522},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11480993032455444}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7705032229423523},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6421206593513489},{"id":"https://openalex.org/C2164484","wikidata":"https://www.wikidata.org/wiki/Q5170150","display_name":"Core (optical fiber)","level":2,"score":0.5835827589035034},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.44351664185523987},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.39895516633987427},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.23211663961410522},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11480993032455444}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/smartnets58706.2023.10215714","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/smartnets58706.2023.10215714","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 International Conference on Smart Applications, Communications and Networking (SmartNets)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4000000059604645,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":28,"referenced_works":["https://openalex.org/W808180366","https://openalex.org/W1503638523","https://openalex.org/W1517403092","https://openalex.org/W1539249970","https://openalex.org/W2090150216","https://openalex.org/W2124423341","https://openalex.org/W2179955370","https://openalex.org/W2185342914","https://openalex.org/W2308457092","https://openalex.org/W2395555281","https://openalex.org/W2541206545","https://openalex.org/W2605953901","https://openalex.org/W2619630761","https://openalex.org/W2735827831","https://openalex.org/W2740230064","https://openalex.org/W2809585638","https://openalex.org/W2905786656","https://openalex.org/W2950271523","https://openalex.org/W3002188027","https://openalex.org/W3033299617","https://openalex.org/W3085407124","https://openalex.org/W3120615272","https://openalex.org/W3128822835","https://openalex.org/W3194242682","https://openalex.org/W3217323659","https://openalex.org/W4285304708","https://openalex.org/W6678461214","https://openalex.org/W6800214491"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W2748952813","https://openalex.org/W2111241003","https://openalex.org/W2390279801","https://openalex.org/W2358668433","https://openalex.org/W2355315220","https://openalex.org/W2096844293","https://openalex.org/W2363944576","https://openalex.org/W2351041855","https://openalex.org/W2570254841"],"abstract_inverted_index":{"Nowadays\u2019":[0],"great":[1,10],"emphasis":[2],"on":[3],"data":[4],"security":[5,42,68,117],"has":[6],"led":[7],"to":[8,17,29,35,96,211],"a":[9,47,57,109,113,128,146],"need":[11,28],"for":[12,40,112,163],"hardware":[13,26],"accelerated":[14],"cryptograhic":[15],"algorithms":[16],"cope":[18],"with":[19,86],"the":[20,73,79,107,153,164,181,189,194],"high":[21],"communication":[22],"bandwidth":[23],"demand.":[24],"These":[25],"accelerators":[27],"be":[30,84,125],"highly":[31],"tunable":[32,58],"in":[33,72,139,214],"order":[34],"support":[36],"multiple":[37],"operation":[38],"modes":[39,99],"different":[41,98],"applications.":[43,120],"In":[44],"this":[45],"paper,":[46],"Field":[48],"Programmable":[49],"Gate":[50],"Array":[51],"(FPGA)-based":[52],"design":[53,136],"and":[54,67,78,119,161,173,199],"implementation":[55],"of":[56,81,100,104,116,180,197],"Keccak":[59,64],"core":[60,108,123,151],"is":[61,94],"presented.":[62],"The":[63,121,135,150,184],"core\u2019s":[65],"performance":[66],"parameters":[69],"are":[70],"configurable":[71],"sense":[74],"that":[75],"bitrate,":[76],"capacity,":[77],"number":[80],"rounds":[82],"can":[83,124],"user-specified":[85],"an":[87],"extendable":[88],"output":[89],"length.":[90],"Keccak\u2019s":[91],"sponge":[92],"construction":[93],"exploited":[95],"enable":[97],"operation.":[101],"This":[102,204],"level":[103],"flexibility":[105],"makes":[106],"suitable":[110],"fit":[111],"large":[114],"range":[115],"requirements":[118],"implemented":[122,138],"operated":[126],"as":[127],"sponge-based":[129,190],"Pseudo":[130],"Random":[131],"Number":[132],"Generation":[133],"(PRNG).":[134],"was":[137],"VHDL":[140],"(VHSCI":[141],"Hardware":[142],"Description":[143],"Language)":[144],"targeting":[145],"low-cost":[147],"IntelFPGA":[148],"Cyclone-V.":[149],"achieved":[152],"following":[154],"maximum":[155],"throughput":[156],"figures":[157],"of:":[158],"11,":[159],"8.4,":[160],"5.81Gbps":[162],"three":[165],"Secure":[166],"Hash":[167],"Algorithm-3":[168],"(SHA-3)":[169],"variants":[170],"256,":[171],"384,":[172],"512-bit":[174],"respectively,":[175],"while":[176],"occupying":[177],"only":[178],"8%":[179],"FPGA\u2019s":[182],"area.":[183],"random":[185],"sequences":[186],"generated":[187],"by":[188],"PRNG":[191],"successfully":[192],"passed":[193],"National":[195],"Institute":[196],"Standards":[198],"Technology":[200],"(NIST)":[201],"test":[202],"suite.":[203],"paper":[205],"demonstrated":[206],"respectable":[207],"area/performance":[208],"results":[209],"compared":[210],"other":[212],"studies":[213],"literature.":[215]},"counts_by_year":[{"year":2024,"cited_by_count":1}],"updated_date":"2025-12-21T01:58:51.020947","created_date":"2025-10-10T00:00:00"}
